DRAC: Un système de contrôle d'exécution pour multiprocesseur à mémoire partagée

Abstract : The impact of memory hierarchy on the multiprocessor performance is well known. As the technological development of processors is much faster than the one of memories, it has become a widely studied bottleneck. A strong relation between the slow-down on multiprocessor architecture and memory pressure has been identified. Adaptive control system approach can be used to prevent apparition of bottlenecks. This kind of system are based on sensors and actors that implement the mechanism of control. This study intends to identify the relationship between performance slow-down and memory pressure, using hardware performance counters. Based on this relationship, we propose an adaptive control system that improves the efficiency of load balancing among the computer resources. The DRAC system, our adaptive control system, observes the access requests on the memory bus. It then adapts its user-level scheduling strategy to maximize the resource utilization.
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https://tel.archives-ouvertes.fr/tel-00007700
Contributor : Mauricio Pillon <>
Submitted on : Thursday, December 9, 2004 - 4:45:17 PM
Last modification on : Wednesday, July 25, 2018 - 1:24:17 AM
Long-term archiving on : Friday, April 2, 2010 - 8:41:44 PM

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  • HAL Id : tel-00007700, version 1

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Mauricio Pillon. DRAC: Un système de contrôle d'exécution pour multiprocesseur à mémoire partagée. Réseaux et télécommunications [cs.NI]. Institut National Polytechnique de Grenoble - INPG, 2004. Français. ⟨tel-00007700⟩

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