Register Pressure in Instruction Level Parallelism

Sid Touati 1
1 A3 - Advanced analysis to code optimization
UP11 - Université Paris-Sud - Paris 11, Inria Saclay - Ile de France
Abstract : It has become a truism that memory accesses play the major role of degrading program performances. Optimizing compilers must avoid requesting data from memory, if possible, by using the available registers of underlying hardware in the best ways.

This thesis reconsiders the register pressure concept so that it gets higher priority than instruction scheduling, but with full respect to intrinsic fine grain parallelism. We propose to handle register pressure early in code optimization process, before instruction scheduling. Two main strategies are developed. In the first strategy, we handle data dependence graphs (DDG) so that we guarantee register constraints without increasing critical execution paths if possible. We introduce and study the concept of register saturation, which is the exact upper-bound of register need for all valid schedules independently of resource constraints. Its aim is to add some serial arcs to the original DDG such that the worst register need does not exceed the number of available registers. On the other hand, register sufficiency is the exact minimal register requirement. Its aim is to detect unavoidable spilling when it exceeds the number of available registers. After this first analysis pass, any instruction scheduler is free from register constraints and the final allocator would not require avoidable spilling. Our second strategy consists in directly applying an early register allocation while optimizing the performance loss. It is built directly into the input DDG, hence register constraints are fixed before instruction scheduling.

This thesis addresses direct acyclic graphs, acyclic control flow graphs and innermost loops intended for software pipelining. Experimental results show that our heuristics are nearly optimal. This thesis proves that we can and must handle register constraints early in code optimization process while keeping freedom for a further instruction scheduler.
Document type :
Other [cs.OH]. Université de Versailles-Saint Quentin en Yvelines, 2002. English
Contributor : Sid Touati <>
Submitted on : Monday, November 15, 2004 - 3:52:48 PM
Last modification on : Wednesday, June 1, 2016 - 11:29:36 PM
Document(s) archivé(s) le : Thursday, September 13, 2012 - 12:55:23 PM


  • HAL Id : tel-00007405, version 1



Sid Touati. Register Pressure in Instruction Level Parallelism. Other [cs.OH]. Université de Versailles-Saint Quentin en Yvelines, 2002. English. <tel-00007405>




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