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Architectures des Accélérateurs de Traitement Flexibles pour les Systèmes sur Puce

Pascal Benoit 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : The systems -on-chip integrate on a same silicon die the whole set of cores necessary to handle the various functionalities of the system. For the digital processing part, the central microprocessor is often discharged from the time consuming applications (generally, digital signal processing applications) by a processing accelerator. The thesis problematic stands-on the architecture of this coprocessor. Indeed, many approaches are possible for it, and comparing them is proved to be a complex task. After a state of the art of the various architectural solutions for flexible processing, we propose a whole set of metrics with a perspective of characterization. Then, we illustrate our method by the characterization and the comparison of architectures representative of the state of the art. We show that it is by an effective exploitation of parallelism that the coprocessors can improve significantly their performances. However, in spite of real aptitudes, the accelerators are not always able to benefit from this potential. From this observation, we propose a general method based on hardware multiplexing, allowing effective loop and task parallelism exploitation. By its application to a concrete case, a system named Saturn, we prove that by the addition of a controller dedicated to the hardware multiplexing, the performances of the accelerator are almost doubled, without hardware overcost.
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Submitted on : Tuesday, November 9, 2004 - 3:11:55 PM
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Pascal Benoit. Architectures des Accélérateurs de Traitement Flexibles pour les Systèmes sur Puce. Micro et nanotechnologies/Microélectronique. Université Montpellier II - Sciences et Techniques du Languedoc, 2004. Français. ⟨tel-00007352⟩

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