Abstract : The continuous evolution of integrated circuits technology is challenging designers to shift from application-specific components (ASIC) to full systems on a single chip (SoC). In order to manage the complexity of these SoC systems, they are built by assembling pre-designed components from different providers. Moreover, a complete SoC design flow requires the integration of several design tools from different providers and for different application domains. The integration of these heterogeneous components into a single system is very difficult, requiring an adaptation of their interfaces to the embedded communication network. This adaptation often needs sophisticated interface sub-systems, that can also be constructed by assembling pre-designed interface components. Integrating design tools from different providers into a complete SoC design flow is also a difficult task, requiring seamless interoperability among the different tools. Handling tool and component integration on a complete SoC design flow is a fastidious, error-prone, and time-consuming manual work. Due to the always increasing time-to-market pressure,, an open environment for the automation of tool and component integration is becoming crucial. The main contribution of this thesis is the definition of an open environment for component/tool integration built around an intermediate format. This environment eases design tool integration according to a well-defined model. It also defines a generic design flow and composition techniques for hardware/software component integration. The proposed concepts were validated using two case-studies: the integration of Cadence VCC design tool and of a communication IP, described in a high abstraction level, into the ROSES design flow.