Skip to Main content Skip to Navigation
Theses

Modélisation, simulation et vérification de circuits numériques asynchrones dans le standard SystemC v2.0.1

Abstract : ITRS 2003 forecasts importance of asynchronous digital design style growth with digital system complexity increase and technology shrinking. From a theoretical perspective, discrete event systems encompass asynchronous digital circuits. A necessary and sufficient condition to abstract delays from an asynchronous digital circuit specification is the guarantee of delay insensitive properties, namely persistence, safety and liveness. From a practical perspective, SystemC v2.0.1 digital system design standard is targeted and adapted to support asynchronous digital circuits modeling and simulation, including delay insensitive properties verification. The model is validated on small but significant examples. Finally, perspective opens out. First, a finer theoretical study should be lead. Second, SystemC v2.0.1 standard should evolve to integrate asynchronous discrete event systems semantics. Third, the model of asynchronous digital circuits based on SystemC v2.0.1 should be improved. At last, asynchronous digital design flow based on SystemC v2.0.1 should be completed with formal verification, circuit synthesis and test.
Complete list of metadatas

Cited literature [26 references]  Display  Hide  Download

https://tel.archives-ouvertes.fr/tel-00006454
Contributor : Lucie Torella <>
Submitted on : Tuesday, July 13, 2004 - 1:31:52 PM
Last modification on : Thursday, November 19, 2020 - 3:56:18 PM
Long-term archiving on: : Friday, April 2, 2010 - 8:40:30 PM

Identifiers

  • HAL Id : tel-00006454, version 1

Collections

TIMA | CNRS | UGA

Citation

A. Sirianni. Modélisation, simulation et vérification de circuits numériques asynchrones dans le standard SystemC v2.0.1. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2004. Français. ⟨tel-00006454⟩

Share

Metrics

Record views

335

Files downloads

4242