H. Martinez-reyes, G. Quadri, T. Parenty, C. Gonzalez, B. Benazet et al., Optically synchronized oscillators for low phase noise microwave and RF frequency distribution, 33rd European Microwave Conference, EuMC'03, pp.1413-1416, 2003.
DOI : 10.1109/eumc.2003.177753

]. Y. Mat_00, T. Matsuoka, and . Ishibashi, High-speed optical devices for 40 Gbit/s optical receivers, Optical Fiber Communication Conference, OFC'00, pp.251-253, 2000.

M. Meghelli, B. Parker, H. Ainspan, and M. Soyuer, SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems, IEEE Journa l of Solid-State Circuits, vol.35, issue.12, 1992.

J. G. Denis and . Mestdagh, Fundamentals of Multiaccess Optical Fiber Networks, 1995.

Y. Miyamoto, M. Yoneyama, T. Otsuji, K. Yonenaga, and N. Shimizu, 40-Gbit/s TDM transmission technologies based on ultra-high-speed ICs, IEEE Journal of Solid-State Circuits, vol.34, issue.9, pp.1246-1253, 1999.
DOI : 10.1109/4.782083

Y. Miyamoto, M. Yoneyama, K. Hagimoto, T. Ishibashi, and N. Shimizu, 40 Gbit/s high sensitivity optical receiver with uni-travelling-carrier photodiode acting as decision IC driver, Electronics Letters, vol.34, issue.2, pp.214-215, 1998.
DOI : 10.1049/el:19980131

M. Muller, S. Withitsoonthorn, M. Riet, J. L. Benchimol, and C. Gonzalez, Millimeter-wave InP/InGaAs photo-HBT and its application to optoelectronic integrated circuits, IEICE Transactions on Electronics, issue.7, pp.1299-1310, 2003.

M. Muller, M. Riet, C. Fortin, S. Withitsoonthorn, J. Orgeval et al., Millimetrewave InP/InGaAs photo-HBT and its application to a double -stage cascode optoelectronic mixer, International Topical Meeting on Microwave Photonics, pp.2345-348, 2002.
DOI : 10.1109/mwp.2002.1158934

]. K. Mur_01, T. Murata, Y. Enoki, E. Yamane, and . Sano, High speed optical fiber communication ICs based on InP HEMT, IEEE International Conference On Indium Phosphide and Related Materials, IPRM'01, pp.610-613, 2001.

Y. Muramoto, K. Kato, M. Mitsuhara, O. Nakajima, Y. Matsuoka et al., High-output-voltage, high speed, high efficiency uni-travelling-carrier waveguide photodiode, Electronics Letters, vol.34, issue.1, pp.122-123, 1998.
DOI : 10.1049/el:19980054

H. Nosaka, E. Sano, K. Ishii, M. Ida, K. Kurishima et al., A fully integrated 40-Gbit/s clock and data recovery circuit using InP/InGaAs HBTs, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278), pp.83-86, 2002.
DOI : 10.1109/MWSYM.2002.1011564

]. T. Ohn_00, S. Ohno, Y. Fukushima, Y. Doi, Y. Muramoto et al., Transmission of millimeterwave signals in a fiber-radio system using a unitraveling-carrier waveguide photodiode, IEEE Photonics Technology Letters, vol.12, issue.10, pp.1379-1381, 2000.

]. T. Ots_97, Y. Otsuji, E. Imai, S. Sano, S. Kimura et al., 40-Gb/s ICs for future lightwave communications systems, IEEE Journal of Solid-State Circuits, vol.32, issue.9, pp.1363-1370, 1997.

]. A. Pot_94, U. Pottbacker, and . Langmann, A 8 GHz silicon bipolar clock-recovery and data-regenerator IC, IEEE International Solid-State Circuits Conference Digest of Technical Papers, 41st ISSCC'94, pp.116-117, 1994.

]. D. Références-[-abr_02 and . Abramovich, Phase-locked loops : A control centric tutorial, Proceedings of the American Control Conference, 2002.

J. D. Alexander, Clock recovery from random binary signals, Electronics Letters, vol.11, issue.22, pp.541-542, 1975.
DOI : 10.1049/el:19750415

D. Baek, J. Kim, and S. Hong, A Ku band InGaP/GaAs HBT MMIC VCO with a balanced and a differential topologies, IEEE MTT-S International Microwave Symposium Digest, vol.2, pp.847-850, 2002.

R. E. Best, Phase-Locked Loops : Design, Simulation & Applications " 3 rd edition, 1997.

]. D. Bri_94, G. Briggmann, U. Hanke, A. Langmann, and . Pottbacker, Clock recovery circuits up to 20

M. E. Elrabaa, An all-digital clock recovery and data retiming circuitry for high speed NRZ d ata communications, IEICE Transactions on Electronics, issue.5, pp.1170-1176, 2002.

S. Finocchiaro, G. Palmisano, R. Salerno, and C. Sclafani, Design of bipolar RF ring oscillators, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), pp.5-8, 1999.
DOI : 10.1109/ICECS.1999.812210

]. F. Gar_80 and . Gardner, Charge-Pump Phase-Lock Loops, IEEE Transactions on, vol.28, issue.11, pp.1849-1858, 1980.

M. Floyd and . Gardner, PhaseLock Techniques, 1979.

G. Georgiou, Y. Baeyens, C. Young-kai, A. H. Gnauck, C. Gropper et al., Clock and data recovery IC for 40-Gb/s fiber-optic receiver, IEEE Journal of Solid-State Circuits, vol.37, issue.9, pp.1120-1125, 2002.
DOI : 10.1109/jssc.2002.801186

]. Y. Gre_00b, P. Greshishchev, and . Schvan, SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application, IEEE Journal of Solid-State Circuits, vol.35, issue.9, pp.1353-1359, 2000.

]. Y. Gre_00, P. Greshishchev, J. L. Schvan, X. Showell, J. J. Mu-liang et al., A fully integrated SiGe receiver IC for 10-Gb/s data rate, IEEE Journal of Solid-State Circuits, vol.35, issue.12, pp.1949-1957, 2000.

. C. Jr and . Hogge, A self correcting clock recovery circuit, Journal of Lightwave Technology, vol.3, issue.6, pp.1312-1314, 1985.

]. K. Ish_02, K. Ishii, H. Kishine, and . Ichino, A jitter suppression technique for a 2.48832-Gb/s clock and data recovery circuit, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, [see also IEEE Transactions on Circuits and Systems II: Express Briefs], pp.266-272, 2002.

]. N. Ish_94, Y. Ishihara, and . Akazawa, A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample -and-hold technique, IEEE Journal of Solid-State Circuits, vol.29, issue.12, pp.1566-1571, 1994.

]. K. Kis_02, K. Kishine, H. Ishii, and . Ichino, Loop-parameter optimization of a PLL for a low-jitter 2.5- Gb/s one-chip optical receiver IC with 1: 8 DEMUX, IEEE Journal of Solid-State Circuits, vol.37, issue.1, pp.38-50, 2002.

]. K. Kis_99, N. Kishine, K. Ishihara, H. Takiguchi, and . Ichino, A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs, IEEE Journal of Solid- State Circuits, vol.34, issue.6, pp.805-812, 1999.

]. T. Lee_00, A. Lee, and . Hajimiri, Oscilltor Phase Noise : A tutorial, IEEE Journal of Solid-State Circuits, vol.35, issue.3, pp.326-336, 2000.

M. J. Mccullagh, A clock recovery and data regeneration sub-system for gigabit optical systems, IEE Colloquium on Gigabit Logic Circuits, vol.5, pp.4-5, 1992.

J. A. Mcneill and R. , A 150 mW, 155 MHz phase locked loop with low jitter VCO, Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS '94, pp.49-52, 1994.
DOI : 10.1109/ISCAS.1994.409099

]. H. Nos_03, E. Nosaka, K. Sano, M. Ishii, K. Ida et al., A 39-to-45- Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector, Symposium on VLSI Circuits Digest of Technical Papers, pp.61-62, 2003.

M. Ramezani and C. A. Salama, An improved bang-bang phase detector for clock and data recovery applications, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), pp.715-718, 2001.
DOI : 10.1109/ISCAS.2001.921956

]. B. Raz_01 and . Razavi, Design of high-speed circuits for optical communication systems, IEEE Conference on Custom Integrated Circuits, pp.315-322, 2001.

]. B. Raz_96 and . Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, 1996.

M. Reinhold, C. Dorschky, E. Rose, R. Pullela, P. Mayer et al., A fully integrated 40-Gb/s clock and data recovery IC with 1:4 DEMUX in SiGe technology, IEEE Journal of Solid-State Circuits, vol.36, issue.12, pp.1937-1945, 2001.
DOI : 10.1109/4.972144

]. V. Sch_01, B. Schwarz, and H. Willen, 56 Gbit/s analogue PLL for clock recovery, Electronics Letters, vol.37, issue.22, pp.1336-1338, 2001.

M. Soyeur and J. D. Warnock, Multigigahertz voltage-controlled oscillators in advanced silicon bipolar technology, IEEE Journal of Solid-State Circuits, vol.27, issue.4, pp.668-670, 1992.
DOI : 10.1109/4.126560

]. S. Sun_89 and . Sun, An analog PLL-based clock and data recovery circuit with high input jitter tolerance, IEEE Journal of Solid-State Circuits, vol.24, issue.2, pp.325-330, 1989.

P. Väänänen, M. Metsänvirta, and N. T. Tchamov, A 4.3-GHz VCO with 2-GHz tuning range and low phase noise, IEEE Journal of Solid-State Circuits, vol.36, issue.1, pp.142-146, 2001.
DOI : 10.1109/4.896240

]. S. Veh_00 and . Vehovic, Clock recovery et gigabit-per-second data rates, Microwave Journal, 2000.

D. Y. Wu, A. C. Yen, D. Meeker, S. Beccue, K. Pedrotti et al., Two phase detectors for 2.5-10 Gb/s NRZ data operation: a Hogge and a balanced mixer, GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996, pp.266-269, 1996.
DOI : 10.1109/GAAS.1996.567884

M. Wurzer, J. Bock, H. Knapp, W. Zirwas, F. Schumann et al., A 40-Gb/s integrated clock and data recovery circuit in a 50-GHz f/sub T/ silicon bipolar technology, IEEE Journal of Solid-State Circuits, vol.34, issue.9, pp.1320-1324, 1999.
DOI : 10.1109/4.782092

R. Yu, R. Pierson, P. Zampardi, K. Runge, A. Campana et al., Packaged clock recovery integrated circuits for 40 Gbit/s optical communic ation links, 18th Annual Gallium Arsenide Integrated Circuit Symposium, GaAs IC'96, pp.129-132, 1996.
DOI : 10.1109/gaas.1996.567824

Z. Liyang, R. Pullela, C. Winczewski, J. Chow, D. Mensa et al., A 37???50 GHz InP HBT VCO IC for OC-768 fiber optic communication applications, 2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280), pp.285-88, 2002.
DOI : 10.1109/RFIC.2002.1011929

H. Zhong and S. I. Long, Site internet " www.ucop, Final Report, 1998.

D. Baek, J. Kim, and S. Hong, A Ku band InGaP/GaAs HBT MMIC VCO with a balanced and a differential topologies, IEEE MTT-S International Microwave Symposium Digest, vol.2, pp.847-850, 2002.

R. Baeyens, C. Pullella, J. Dorschky, R. Mattia, H. Kopf et al., Compact differential InP-based HBT VCO's with a wide tuning range at W-band, 2000 IEEE MTT-S International Microwave Symposium Digest (Cat. No.00CH37017), pp.349-352, 2000.
DOI : 10.1109/MWSYM.2000.861012

]. A. Bes_98 and . Bessemoulin, Contribution à la modélisation de structures coplanaires en technologie monolithique, Thèse de doctorat, 1998.

]. S. Bla_03, M. Blayac, M. Kahn, P. Riet, J. Berdaguer et al., Simple and accurate method to extract intrinsic and extrinsic base-collector capacitance of bipolar transistors, Electronics Letters, vol.39, issue.7, pp.1282-1283, 2003.

]. S. Bla_00 and . Blayac, Transistor bipolaire à double hétérojonction InP/InGaAs pour circuits de communications optiques à très haut débit, Thèse de doctorat, 2000.

]. D. Caf_96 and . Caffin, Filière technologique TBH InP/InGaAs pour applications aux systèmes de communications à haut débit, Thèse de doctorat, 1996.

]. L. Cam_96, S. Camnitz, T. Kofol, S. R. Low, and . Bahl, An accurate, large signal, high frequency model for GaAs HBTs, 18th Annual Gallium Arsenide Integrated Circuit Symposium, GaAs IC'96, pp.303-306, 1996.

A. Dearn, "How to design RF circuits" - oscillators, IEE Colloquium on How to Design RF Circuits, 2000.
DOI : 10.1049/ic:20000146

J. K. Everard, Low Noise Oscillators a Review, IEE Colloquium on Microwave and Millimetre-Wave Oscillators and Mixers (Ref, vol.48010, issue.1, pp.1-1, 1998.

K. C. Gupta, R. Garg, I. Bahl, and P. Bhartia, Microstrip Lines and Slot Lines, 1996.

]. T. Lee_00, A. Lee, and . Hajimiri, Oscilltor Phase Noise : A tutorial, IEEE Journal of Solid-State Circuits, vol.35, issue.3, pp.326-336, 2000.

]. S. Lon_90, S. E. Long, and . Butner, GaAs Digital Integrated Circuit Design, 1990.

J. Mba, Fabrication, caractérisation et modélisation des transistors bipolaires à double hétérojonction InP pour circuits de communications optiques à très haut débit (40 Gbit/s), Thèse de doctorat, 1999.

]. B. Raz_96 and . Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, 1996.

]. G. Ree_82 and . Reeves, Obtaining the specific contact resistance from transmission line model measurements, IEEE electron device letters, vol.3, issue.5, pp.111-112, 1982.

M. Riet, S. Blayac, J. Benchimol, P. André, P. Berdaguer et al., Self-aligned InP/InGaAs double heterojunction bipolar transistors for high bit-rate circuit applications, Proceedings of Wocsdice, 1999.

J. W. Rogers and C. Plett, Radio Frequency Integrated Circuit Design, 2003.

J. W. Rogers, J. A. Macedo, and C. Plett, The effect of varactor nonlinearity on the phase noise of completely integrated VCOs, IEEE Journal of Solid-State Circuits, vol.35, issue.9, pp.1360-1367, 2000.
DOI : 10.1109/4.868048

]. D. She_03, S. Shaeffer, and . Kudszus, Performance-optimized microstrip coupled VCOs for 40-GHz and 43-GHz OC-768 optical transmission, IEEE Journal of Solid-State Circuits, vol.38, issue.7, pp.1130-1138, 2003.

H. Paul and . Young, Electronic Communication Techniques, 1999.

J. C. Zhan, K. Maurice, J. Duster, and K. T. Kornegay, Analysis and design of negative impedance LC oscillators using bipolar transistors, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications [see also IEEE Transactions on Circuits and Systems I: Regular Papers], pp.1461-1464, 2003.

. Manuel-d-'utilisation, Analyseur de Spectre HP8560 série E, 1994.

J. S. Foord, G. J. Davies, and W. T. Tsang, Gas Source Molecular Beam Epitaxy, 1997.

]. P. Gra_01, P. J. Gray, S. H. Hurst, R. G. Lewis, and . Meyer, Analyse and Design of Analog Integrated Circuits, 2001.

]. A. Kur_02, M. Kurdoghlian, C. H. Mokhtari, S. Fields, and I. Thomas, 44 GHz fully integrated and differential monolithic VCOs with wide tuning range in AlInAs/InGaAs/InP DHBT, 24th Annual Technical Digest Gallium Arsenide Integrated Circuit Symposium,GaAs IC'02, pp.287-290, 2002.

]. H. Li_02, H. Li, R. Rein, W. Kreienkamp, and . Klein, 47 GHz VCO with low p hase noise fabricated in a SiGe bipolar production technology, IEEE Microwave and Wireless Components Letters, vol.12, issue.3, pp.79-81, 2002.

]. V. Sch_01, B. Schwarz, and H. Willen, 56 Gbit/s analogue PLL for clock recovery, Electronics Letters, vol.37, issue.22, pp.1336-1338, 2001.