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Theses

Applications des boucles à verrouillage de délais à la synthèse de fréquences dans les circuits pour communications mobiles

Abstract : Semiconductors firms aim to simplify design, production processes which are nowadays still costly because of complexity reason. The goal of this thesis work is to study the opportunity of designing frequency synthesisers with MOS transistors, for analogue application (Local oscillator, clock for analogue to digital or digital to analogue converters). We propose the study of two frequencies synthesisers based on Delay-Locked-Loop. Those have the advantage of having an integrated loop filter.
One multiplies the frequency of a reference signal by an integer. Although general principles have already been done, we propose a better understanding about phase noise of the generated signal and we derive a more accurate expression of its spectra formula. We demonstrate the opportunity of using such a synthesiser as an intermediate frequency local oscillator in a heterodyne architecture for a GSM application.
The architecture of the other synthesiser is original. We get programmable frequencies synthesisers. The output frequency is due to the multiplication of the reference frequency and a rational number. The results fit well with the depicted theory. Its features allow applications as clock in mobile communication systems.
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Theses
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https://tel.archives-ouvertes.fr/tel-00005765
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Submitted on : Monday, April 5, 2004 - 6:02:31 PM
Last modification on : Monday, August 3, 2020 - 5:20:02 PM
Long-term archiving on: : Friday, April 2, 2010 - 9:08:19 PM

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  • HAL Id : tel-00005765, version 1

Citation

Olivier Susplugas. Applications des boucles à verrouillage de délais à la synthèse de fréquences dans les circuits pour communications mobiles. Autre. Ecole nationale supérieure des telecommunications - ENST, 2004. Français. ⟨tel-00005765⟩

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