Abstract : Today, ASIC macro-cells dedicated to signal digital processing (DSP-ASIC macro-cells in follow) become more and more complex. Their design requires much time and money. These DSP-ASIC macro-cells will be assembled with other components to build the required Multiprocessor System-On-Chip (MP-SoC). The current design processes become insufficient to master the increasing complexity (in term of algorithm and architecture) while meeting the design time requirements.
This Ph-D thesis targets the problem of the design and the validation of DSP-ASIC macro-cells. We study the possibilities of a new methodology that could be used as an alternative to high level synthesis. This methodology is based on the assembly of basic generic predesigned components (IPs). It starts from a functional description of the application and produces an RTL model of the final architecture. The main problem of a component based assembly methodology is that the RTL model can have dysfunctions. This is due to delays introduced by implementation constraints. We present the formalization of this problem and propose an automatic correction method (called delay correction method) to resolve it. The viability of the method and the optimality of the solution are mathematically proved. Tools have been implemented to transform the methodology into a semi-automatic flow. We illustrate the approach efficiency by experiment on an industrial example: a digital modulation chain.