Construction de Modèles Réduits et Vérification Symbolique de Circuits Industriels décrits au Niveau RTL

Abstract : Symbolic model checking applied to hardware designs is limited by the exponential complexity in the size of the underlying verified model. This work explores several issues for achieving model-reduction, either manually or on an automated basis. The structural and behavioral approaches of compositional verification have been studied in an industrial design context. This study has enabled the development of a new model reduction technique : the functional partitionning. This technique is intended for those systems whose behavior can be sequentially decomposed. It relies on a preliminary simbolic simulation step which is performed prior to the actual verification. Functional partitionning has been implemented and applied on an industrial design of non-trivial size and shows spectacular model-reduction results. In support of the experiments presented here, a VHDL to finite state machines translator tool has been developed and used.
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Micro and nanotechnologies/Microelectronics. Université Joseph-Fourier - Grenoble I, 2003. French


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Submitted on : Friday, October 31, 2003 - 10:31:58 AM
Last modification on : Thursday, February 16, 2006 - 9:11:31 AM

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E. Dumitrescu. Construction de Modèles Réduits et Vérification Symbolique de Circuits Industriels décrits au Niveau RTL. Micro and nanotechnologies/Microelectronics. Université Joseph-Fourier - Grenoble I, 2003. French. <tel-00003667>

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