Abstract : Symbolic model checking applied to hardware designs is limited by the exponential complexity in the size of the underlying verified model. This work explores several issues for achieving model-reduction, either manually or on an automated basis. The structural and behavioral approaches of compositional verification have been studied in an industrial design context. This study has enabled the development of a new model reduction technique : the functional partitionning. This technique is intended for those systems whose behavior can be sequentially decomposed. It relies on a preliminary simbolic simulation step which is performed prior to the actual verification. Functional partitionning has been implemented and applied on an industrial design of non-trivial size and shows spectacular model-reduction results. In support of the experiments presented here, a VHDL to finite state machines translator tool has been developed and used.