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Fault injection using run-time reconfiguration of FPGAs

Abstract : Fault injection techniques have been used for a long time to evaluate the dependability of a given hardware, software or system implementation. The basic idea is to deliberately create faults into the environment under test after putting it into operation. The system under test is excited with application test vectors and data are collected on the outputs and also potentially on internal signals. At the end, these data can be used in order to analyse the behaviour of the system when faults occur.
This work focuses on hardware-based fault injections, in digital circuits. In this context, it was proposed to take advantage of hardware prototyping to improve and accelerate the execution of the whole fault injection campaign. Reconfigurable hardware (and especially FPGA devices) is a good candidate to implement the prototypes used to perform fault injections. The reconfiguration of an FPGA can however take a long time and this can be a limitation of prototyping-based techniques, especially if the device must be reconfigured several times. To overcome this problem, the work presented in this thesis aims at taking advantage of partial (also called local) reconfiguration capabilities of the hardware. In this case, only a part of the device must be reconfigured when changes are made. The use of partial reconfiguration capabilities results in an important time gain when only few differences exist between two successive configurations of the FPGA.
Until now, hardware prototyping was used for the execution of the application on faulty versions of the circuit. The fault injection itself was generally made by means of internal logic elements controlled by external signals. These elements were added by modifying either the high level description (e.g. behavioural VHDL) or the gate level description of the circuit, before implementing the prototype. The idea developed in this thesis is not only to execute the application in reconfigurable hardware but also to realise the injection of faults directly in the device (FPGA), taking advantage of the reconfiguration capabilities. Like this, each fault injection (or fault removal) necessitates a partial reconfiguration of the device. On the other hand, the initial description of the system must not be changed before implementing the prototype.
This thesis demonstrates the feasibility of such an approach, for two main types of faults (stuck-at faults and asynchronous bit-flips modelling Single Event Upsets). The injection process using partial reconfiguration has been automated for these types of faults in the case of Virtex-based prototypes. The advantages and limitations with respect to existing techniques have been analysed. Finally, the work concludes on the major parameters that must be optimised to implement an efficient fault injection system based on partial reconfiguration.
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Contributor : Lucie Torella <>
Submitted on : Thursday, September 25, 2003 - 11:51:44 AM
Last modification on : Friday, December 11, 2020 - 8:28:03 AM
Long-term archiving on: : Friday, April 2, 2010 - 7:31:35 PM


  • HAL Id : tel-00003419, version 1




L. Antoni. Fault injection using run-time reconfiguration of FPGAs. Micro and nanotechnologies/Microelectronics. Institut National Polytechnique de Grenoble - INPG, 2003. English. ⟨tel-00003419⟩



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