.. Problématique-d-'intégration-des-mémoires-dans-un-système-monopuce, 18 2.1. L'insuffisance du niveau RTL pour la conception des interfaces logiciel-matériel 18 2.2. Variété des interfaces mémoire et manque de flexibilité d'utilisation Faible production et réutilisation des pilotes d'accès, p.20, 2003.

M. Le-niveau and R. , 21 3.2. Utilisation des interfaces mémoire " produits maison " malgré les efforts de standardisation des interfaces matérielles, Causes et conséquences des problèmes d'intégration 21 3.3. Satisfaction de la conception des systèmes multiprocesseurs classiques par une faible production du logiciel dépendant du matériel

S. Flot-de-conception and .. Des-systèmes-monopuces-avant-son-extension, 56 6.1. Spécification d'entrée du flot de conception, p.57

N. De-bas, Application 99 5.1. Choix de l'application, p.100

.. Architecture-en-couches-d-'un-pilote-logiciel-monopuce, 115 2.1. Architecture logicielle d'un système monopuce, p.119

. Ainsi, les systèmes monopuces avec des mémoires globales sont représentés comme un ensemble de composants virtuels interconnectés via des canaux abstraits (canaux virtuels) La spécification de ces interfaces logiciel-matériel est décrite par le langage Colif. Pour l'implémentation, nous avons été amené à étendre l'environnement du flot SLS pour générer des interfaces spécifiques à la mémoire

C. Et-perspectives-bibliographieabr02, ]. A. Garcia, J. Gobert, T. Dombek, H. Mehrez et al., Energy Estimations in High Level Cycle-Accurate Descriptions of Embedded Systems, Diagnostics of Electronic Circuits and Systems (DDECS'2002), pp.228-235, 2002.

I. Ahmad and C. Y. Chen, Post-processor for data path synthesis using multiport memories, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers, pp.276-279, 1991.
DOI : 10.1109/ICCAD.1991.185252

]. S. Ama95, J. Amarasinghe, M. Anderson, C. Lam, and . Tseng, A Overview of the suif compiler for scalable parallel machines, Processings of the SIAM Conference on Parallel Processing for Scientific Computing, 1995.

S. Mai, D. D. Bakshi, and . Gajski, A memory selection algorithm for high-performance pipelines, com [Bak95] Proceedings of the European Conference EURO-DAC '95 with EURO -VHDL '95 on Design Automation, G. Musgrave, pp.124-129, 1995.

E. Sangiovanni-vincentelli, K. Sentovich, B. Suzuki, ]. P. Tabbaraban95, J. Banerjee et al., Hardware-Software Codesign of embedded System: The Polis Approach The paradigm compiler for distributed-memory multicomputers, IEEE Computer, vol.28, pp.10-37, 1995.

]. I. Bol97, H. J. Bolsens, B. De-man, K. Linn, S. Van-rompaey et al., Hardware/Software co-design of digital telecommunication systems, Proceedings of the IEEE, vol.85, issue.3, pp.391-418, 1997.

]. G. Bor98, L. Borriello, R. B. Lavagno, and . Ortega, Interface synthesis: a vertical slice from digital logic to software components, ICCAD, pp.693-695, 1998.

]. J. Bru00, W. Brunel, H. Kruijtzer, F. Kenter, L. Pétrot et al., COSY Communication IP's, Proc. Of Design Automation Conference, 2000.

]. F. Cat01, N. Catthoor, K. Dutt, S. Danckaert, and . Wuytack, Code Transformation for Data Transfer and Storage Exploration Preprocessing in Multimedia Processor, IEEE Design and Test of Computers, 2001.

]. F. Cat02 and . Catthoor, Data Access and Storage Management for Embedded Programmable Processors, 2002.

]. F. Cat98, S. Catthoor, E. Wuytack, F. Greef, L. Balasa et al., Custom Memory Management Methodology : Exploration of Memory Organization for Embedded Multimedia System Design, Kluwer Academic, 1998.

]. W. Ces01, G. Cesario, L. Nicolescu, D. Geauthier, A. A. Lyonnard et al., Colif: a Multilevel Design Representation for Application-Specific Multiprocessor System-on-Chip Design, 12th IEEE International Workshop on Rapid System Prototyping, 2001.

]. P. Cho99, R. B. Chou, K. Ortega, K. Hines, G. Patridge et al., ipChinook: an Integ rated IPbased Design Framework for Distributed Embedded Systems, DAC, pp.44-49, 1999.

]. K. Dan00, F. Danckaert, H. D. Catthoor, and . Man, A preprocessing step for global loop transformations for data transfer and storage optimization, Proceedings of the International Conference on compilers, Architecture and Synthesis for Embedded Systems, 2000.

]. R. Ern94, . Ernst, . Th, and . Benner, Communication, Constraints and User Directives in COSYMA, 1994.

]. M. Fly72 and . Flyn, Some computer organizations and their effectiveness, IEEE Transactions on Computers, issue.21, pp.948-960, 1972.

]. A. Fra01 and . Fraboulet, Optimisation de la mémoire et de la consommation des systèmes multimédia embarqués, Thèse : Institut National des sciences appliquées de Lyon, 2001.

]. A. Fra01, K. Fraboulet, A. Kodray, and . Mignotte, Loop Fusion for Memory Space Optimization, Procedings of Internal Syposium on System Synthesis, 2001.

]. F. Fra94, L. Franssen, H. Nachtergaele, F. Samson, . Catthoor et al., Control flow optimization for fast system simulation and storage minimization, Proceedings of the International Conference on Design and Test, pp.20-24, 1994.

]. D. Gaj98, F. Gajski, S. Vahid, J. Narayan, and . Gong, SpecSyn: An Environment Supporting the Specify-Explore-Refine Paradigm for Hardware/Software System Design, IEEE Transactions on VLSI Systems, vol.6, issue.1, 1998.

]. L. Gau01 and . Gauthier, Génération de système d'exploitation pour le ciblage de logiciel multitâche sur des architectures multiprocesseurs hétérogènes dans le cadre des systèmes embarqués spécifiques, Thèse de doctorat, 2001.

]. F. Gha00 and . Gharsalli, Conception mixte logicielle/matérielle des systèmes multiprocesseurs avec mémoire, DEA informatique systèmes et communication, 2000.

F. Gharsalli, D. Lyonnard, S. Meftali, F. Rousseau, and A. A. Jerraya, Unifying memory and processor wrapper architecture in multiprocessor SoC design, Proceedings of the 15th international symposium on System Synthesis , ISSS '02, 2002.
DOI : 10.1145/581199.581207

URL : https://hal.archives-ouvertes.fr/hal-00008060

F. Gharsalli, S. Meftali, F. Rousseau, and A. A. Jerraya, Automatic generation of embedded memory wrapper for multiprocessor SoC, proceedings of the 39th Design Automation Conference (DAC'02), pp.596-601, 2002.
URL : https://hal.archives-ouvertes.fr/hal-00008063

]. E. Gre95, F. Greef, H. Catthoor, and . Man, Memory organization for video algorithms on programmable signal processors, Proceedings of the IEEE International Conference on computer Design (ICCD '95, pp.552-557, 1995.

]. P. Gue00, A. Guerrier, and . Greiner, A generic architecture for on-chip packet switched interconnections, proceedings of Design Automation and Test in Europe, 2000.

]. J. Hen99, M. Hennessy, A. Heinrich, and . Gupta, Cache-Coherent Distributed Share Memory : Perspectives on Its Development and Future Challenges, Special issue on distributed Shared-Memory Systems, 1999.

. Ibm02 and . Ibm, The CoreConnect Bus Architecture " available at: http://www.chips.ibm.com/products, 2002.

T. B. Ismail, J. Daveau, K. O-'brien, and A. A. Jerraya, A system-level communication synthesis approach for hardware/software systems, Microprocessors and Microsystems, vol.20, issue.3, pp.1076-1993149, 1993.
DOI : 10.1016/0141-9331(95)01072-6

URL : https://hal.archives-ouvertes.fr/hal-00008163

]. D. Jen97, J. Jensen, S. Madsen, and . Pedersen, The importance of Interfaces: A HW/SW codesign case study, Preceedings of 5 th International Workshop on Codesign, 1997.

]. A. Jer02 and . Jerraya, De l'ASIC au SoC, puis au réseau de composants sur puce, 2002.

]. P. Jha97, N. Jha, and . Dutt, Library mapping for memories, Proceedings European Design and Test Conference. ED & TC 97, pp.288-317, 1997.
DOI : 10.1109/EDTC.1997.582372

]. D. Kar94, J. Karchmer, and . Rose, Definition and solution of the memory packing problem for fieldprogrammable systems, Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design (ICCAD '94, pp.20-26, 1994.

]. T. Kat99, K. Katayama, A. Saisho, and . Fukuda, Proposal of a Support System for Device Driver Generation, Proc. Asia-Pacific Softw. Eng. Conf. (APSEC'99), pp.494-497, 1999.

]. W. Kel92, W. Kelly, and . Pugh, Generating schedules and code within a unified reordering transformation framework, 1992.

T. Kim and C. L. Liu, Utilization of multiport memories in data path synthesis, Proceedings of the 30th international on Design automation conference , DAC '93, pp.298-302, 1993.
DOI : 10.1145/157485.164900

]. P. Knu98, J. Knudsen, and . Madsen, Integrating Communication Protocol Selection with Hardware/Software Codesign, ISSS, 1998. (lycos) [Kus94] J. Kuskin et al Proceedings of the 21st Int'l Symposium On Computer Architecture, 1994.

]. D. Lov77 and . Loveman, Program improvement by source-to-source transformation, J. ACM, vol.24, pp.121-145, 1977.

]. D. Lyo01, S. Lyonnard, A. Yoo, A. A. Baghdadi, and . Jerraya, Automatic Generation of Application- Specific Architectures for Heterogeneous Multiprocessor System-on-Chip, Proceedings DAC, 2001.

]. D. Lyo03 and . Lyonnard, Approche d'assemblage systématique d'éléments d'interface pour la génération d'architectures multiprocesseurs, Thèse de doctorat, 2003.

]. K. Mas99, F. Masselos, C. Catthoor, H. D. Goutis, and M. , A performance oriented use methodology of power optimizing code transformations for multimedia applications realized on programmable multimedia processors, Proceedings of the IEEE Workshop on Signal Processing Systems, pp.270-272, 1999.

]. K. Mck98 and . Mckinley, A compiler optimization algorithm for shared-memory multiprocessors, IEEE Trans. Parallel Distrib. Syst, vol.9, issue.8, pp.769-787, 1998.

]. S. Mef01a and . Meftali, Exploration d'architectures et allocation/affectation mémoire dans les systèmes multiprocesseurs monopuce, Thèse de doctorat, 2001.

]. S. Mef01b, F. Meftali, F. Gharsalli, A. A. Rousseau, and . Jerraya, An Optimal Memory Allocation for Application-Specific Multiprocessor System-on-Chip, Proc. Int'l Symposium on System Synthesis (ISSS), 2001.

R. Philip, R. Moorby, and D. E. Thomas, The Verilog Hardware Description Language, 1998.

]. E. Nic02 and . Nicolescu, Spécification et validation des systèmes hétérogènes embarqués, Thèse de doctorat, 2002.

]. R. Nie98 and P. Niemann, Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems, Design, Automation and Test in Europe (DATE), 1998.

J. Öberg, A. Kumar, and H. , Grammer based hardware synthesis of data communication protocols, Proceedings of the 9 th International Symposium on System Synthesis, pp.14-19, 1996.

]. M. Oni01, A. J. O-'nils, and . Jantsch, Device Driver and DMA Controller Synthesis from HW/SW Communication Protocol Specifications, Design Automation for Embedded Systems, 2001.

]. M. Oni98, J. O-'nils, A. J. Öberg, and . Jantsch, Grammar Based Modelling and synthesis of device drivers and bus interfaces, Proc. of the EuroMicro Workshop on Digital System Design, 1998.

. Opencore, Protocol International Partnership

]. P. Pan00, N. D. Panda, A. Dutt, and . Nicolau, On-chip vs. off-chip memory: The data portioning problem in embedded processor-based systems, ACM Trans. Des. Autom. Electron. Syst, vol.53, pp.682-704, 2000.

P. G. Vandercappelle and . Kjeldsberg, Data and memory optimization techniques for embedded systems, TODAES, vol.6, issue.2, pp.149-206, 2001.

]. P. Pan96, N. D. Panda, A. Dutt, and . Nicolau, Memory organization for improved data cache performance in embedded processors, Proceedings of the ACMIIEEE International Symposium on System Synthesis, pp.90-95, 1996.

]. D. Pat98, J. L. Patterson, and . Hennessy, Computer Organization and Design -The Hardware/Software Interface, 1998.

]. J. Pro96, M. Protic, V. Tomasevic, and . Milutinovic, Distributed Shared Memory : Concepts and Systems, IEEE Parallel & Distributed, 1996.

]. H. Tag00 and . Tago, CPU for Playstation 2, Workshop on synthesis and System integration pf Mixed technology (SASIMI), 2000.

H. Tomiyama and H. Yassuura, Size-constrained code placement for cache miss rate reduction, Proceedings of 9th International Symposium on Systems Synthesis, pp.96-101, 1996.
DOI : 10.1109/ISSS.1996.565887

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.53.1767

. Jerraya, A unified model for co-simulation and co-synthesis of mixed hardware/software systems, pp.579-583, 2001.
URL : https://hal.archives-ouvertes.fr/hal-01467291

]. S. Ver96, B. Vercauteren, H. Lin, and . De-man, Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications, Proc. of DAC, 1996.

]. P. Wil95, M. Wilson, M. Jhonstone, D. Neely, and . Boles, Dynamic storage allocation : A survey and critical review, Vsi02] Virtual Socket Interface Alliance proceedings of the International Workshop on Memory Management, 1995.

]. M. Wol91, M. S. Wolfe, and . Lam, A loop transformation theory and an algorithm to maximize parallelism, IEEE Trans. Parallel Distrib. Syst, vol.2, issue.4, pp.452-471, 1991.

F. Gharsalli, S. Meftali, F. Rousseau, and A. A. Jerraya, Automatic generation of embedded memory wrapper for multiprocessor SoC, www.w3c.org/XML Publications PUBLICATIONS 1 proceedings of the 39th Design Automation Conference (DAC'02), pp.596-601, 2000.
URL : https://hal.archives-ouvertes.fr/hal-00008063

F. Gharsalli, D. Lyonnard, S. Meftali, F. Rousseau, and A. A. Jerraya, Unifying memory and processor wrapper architecture in multiprocessor SoC design, Proceedings of the 15th international symposium on System Synthesis , ISSS '02, 2002.
DOI : 10.1145/581199.581207

URL : https://hal.archives-ouvertes.fr/hal-00008060

S. Meftali, F. Gharsalli, F. Rousseau, and A. A. Jerraya, An optimal memory allocation for applicationspecific multiprocessor system-on-chip, proceedings of the 13th International Symposium on System Synthesis, pp.19-24, 2001.
URL : https://hal.archives-ouvertes.fr/hal-00008071

S. Meftali, F. Gharsalli, F. Rousseau, and A. A. Jerraya, Automatic code-transformations and architecture refinement for application-specific SoC, proceedings of IFIP International Conference on Very Large Scale Integration Conference (VLSI-SOC 2001), 2001.

S. Meftali, F. Gharsalli, F. Rousseau, A. A. Jerraya, and C. Dans-un-livre, Architecture refinement for application-specific multiprocessor SoC, Kluwer, 2002.
DOI : 10.1007/978-0-387-35597-9_17