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Theses

Vérification formelle des résultats de la synthèse de haut niveau

Abstract : To satisfy the present market requirements, several commercial formal verification tools appeared recently. The highest description level accepted by these tools is the so-called Register Transfer Level, i.e. with clearly identified clock periods. Because of very strong competition the designers must, however, start
from more abstract initial descriptions and use high-level synthesis tools. This thesis addresses the formal verification of high-level synthesis results with respect to the initial specification given in VHDL.
We propose a methodology that follows the design flow and includes the verification of two main synthesis steps: scheduling and allocation. The verification of each step is based on an abstract machine model that we developed: contrary to the classic finite state machine, it
reduces considerably the state space by keeping the data path registers symbolic. Moreover, the similarity between the abstract machine and the VHDL description provides facilities for the model construction
and understanding. The proof of the equivalence between abstract and classical finite state machines justifies the abstract machine and constitutes one of the theoretical contributions of the thesis. A prototype tool based on symbolic execution was developed and applied
to some high-level synthesis benchmarks. Finally, the thesis points out some open problems and suggests some research directions to solve them
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Submitted on : Monday, June 16, 2003 - 2:51:38 PM
Last modification on : Friday, December 11, 2020 - 8:28:03 AM
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  • HAL Id : tel-00003009, version 1

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J. Dushina. Vérification formelle des résultats de la synthèse de haut niveau. Autre [cs.OH]. Université Joseph-Fourier - Grenoble I, 1999. Français. ⟨tel-00003009⟩

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