]. R. Références-diverses, S. P. Acosta, . Smith, and . Larson, Mixed-Mode Simulation of Compiled VHDL Programs, IEEE International Conference on Computer-Aided Design ICCAD'89, pp.176-179, 1989.

V. D. Agrawal and S. T. Chakradhar, Logic simulation and parallel processing, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, pp.496-499, 1990.
DOI : 10.1109/ICCAD.1990.129963

A. Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka et al., Test program generation for functional verification of PowerPC processors in IBM, Proceedings of the 32nd ACM/IEEE conference on Design automation conference , DAC '95, pp.279-285, 1995.
DOI : 10.1145/217474.217542

R. Airiau, J. Bergé, V. Olive, J. B. Rouillard-]-s, and . Akers, VHDL: langage, modélisation, synthèse Binary Decision Diagrams, Presses Polytechniques et Universitaires Romandes et CNET-ENST, Deuxième édition, pp.27-509, 1978.

H. Al-asaad and J. P. Hayes, Design verification via simulation and automatic test pattern generation, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), pp.174-180, 1995.
DOI : 10.1109/ICCAD.1995.480009

T. W. Albrecht, Concurrent design methodology and configuration management of the SIEMENS EWSD-CCS7E processor system simulation, Proceedings of the 32nd ACM/IEEE conference on Design automation conference , DAC '95, pp.222-227, 1995.
DOI : 10.1145/217474.217533

A. A. Ashar, S. Malik, P. I. Ashenden-]-r, E. A. Bahar, C. M. Frohm et al., Fast Functional Simulation Using Branching Programs A Comparison of Recursive and Repetitive Models of Recursive Hardware Structures VHDL International User Forum Spring 1994 VIUF'94 The Designer's Guide to VHDL Algebraic Decision Diagrams and Their Application The Netherlands Simplifying Data Operations for Formal Verification Static Analysis for VHDL Model Evaluation A Reconfigurable Logic Machine for Fast Event-Driven Simulation High-Level Synthesis in a Production Environment VHDL Designer's Reference Sequential Machines and Automata Theory A Tutorial: Formal Methods for VHDL Symbolic Simulation and Verification of VHDL with ACL2 An Approach to Verilog-VHDL Interoperability for Synchronous Designs A Computational Logic Handbook Graph-Based Algorithms for Boolean Function Manipulation, ILC16 ? 16 HDLC Channels Italtel Link Controller Formal Methods in System Design IFIP TC10 WG10.5 International Conference on Computer Hardware Description Languages and their Applications Fundamentals and Standards in Hardware Description Languages, NATO ASI Series, Series E: Applied Science Euro-DAC'94 with Euro-VHDL'94 Conference International HDL Conference HDLCon IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods "CHARME'97, pp.408-412, 1967.

R. Bryant and Y. Chen, Verification of Arithmetic Functions with Binary Moment Diagrams, 1994.

R. Bryant, Y. Chen, J. R. Burch, E. M. Clarke, K. L. Mcmillan et al., Verification of Arithmetic Circuits with Binary Moment Diagrams Sequential Circuit Verification Using Symbolic Model Checking Formal Verification of Hardware Correctness: Introduction and Survey of Current Research, Automation Conference DAC'95 IEEE/ACM Design Automation Conference DAC'90, pp.535-541, 1989.

]. S. Cenelec-report29, J. H. Chandra, Z. Patel-corella, X. Zhou, M. Song et al., VHDL Modeling Guidelines Simulation and Documentation Aspects Accurate Logic Simulation in the Presence of Unknowns The VHDL Handbook The Netherlands VHDL Coding Styles and Methodologies? and In-Depth Tutorial Multiway Decision Graphs for Automated Hardware Verification The Netherlands FPGA Design Flow with Automated Test Generation Binary Decision Diagrams. Theory and Implementation The Netherlands Elements of an Environment For Experiments with High-Level Synthesis " , XVII Krajowa Konferencja Teorii Obwodow i Ukladow Elektronicznych (XVII National Conference on Circuit Theory and Electronic Systems Electronic Industries Association EIA EIA-567A. VHDL Hardware Component Modeling and Interface Standard Project SCADES-2/WP5520 " , document reference ES2 Functional Verification of Large ASICs OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification Multi-Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix Representation Logic, Language, and Meaning Formalisation et validation de paquetages standards VHDL dédiés à la synthèse à l'aide du démonstrateur de théorèmes ACL2 FUTEG Benchmarks Formal Hardware Verification Methods: A Survey VHDL Models for Board-level Simulation Compiled-Code-Based Simulation with Timing Verification Hardware Logic Simulation by Compilation Verification by Simulation Comparison Using Interface Synthesis, Comité Européen de Normalisation Électrotechnique CENELEC TC217/WG2 report 2.14, second draft 11th Workshop on Test Technology and Reliability of Circuits and Systems IEEE/ACM Design Automation Conference DAC'98 Euro-DAC'94 with Euro-VHDL'94 Conference IEEE/ACM Design Automation Conference DAC'88 IEEE Conference on Design Automation and Test in Europe DATE'98, pp.34-37, 1988.

J. L. Hein, . Structures, C. Logic, B. Jones, M. Publishers et al., Finite-State Models for Logical Machines The Logic Automation Approach to Accurate and Efficient Gate and Functional Level Simulation A High Performance VHDL Simulator for Large Systems Design VHDL Experiments on Performance, Euro-DAC'95 with Euro-VHDL'95 Conference Euro- VHDL'91 Conference, pp.250-253, 1968.

D. Humblot, O. Uvre-collective-coordonnée-par-dan-humblot, R. Et-système-d-'information, S. A. Bull, . N. Bull et al., IEEE Std 1164-1993 IEEE Standard VHDL Analog and Mixed-Signal Extensions, IEEE Std 1076.1-1999 IEEE Standard for VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification IEEE Standard for VHDL Register-Transfer Level (RTL) Synthesis Improving Simulation Efficiency by Hierarchical Abstraction Transformations Modeling and Simulation of Computer Systems Based on Abstraction Networks Virtual Chip: Making Functional Models Work On Real Target Systems Integrated Simulation of Performance Models and Behavioral Models Automata-Theoric Verification, IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) Forum on Design Languages FDL'98 IEEE/ACM Design Automation Conference DAC'98 Functional Debugging of Systems-on-Chip IEEE/ACM International Conference on Computer-Aided Design, ICCAD'98 VHDL International User Forum VIUF Fall An Advanced Study Institute of the NATO Science Committee on Verification of Digital and Hybrid Systems, pp.1076-1993, 1076.

T. Lai, S. Sastry, L. Lavagno, A. Sangiovanni-vincentelli, E. Sentovich74 et al., Models of Computation for Embedded System Design " , in System Level Synthesis, NATO Science Series The Netherlands APEX Atomic Property EXtractor for full VHDL. Implementor's Guide, Version 1 LVS Implementor's Guide: VHDL*Verilog Intermediate Format (VIF), Version 4 VHDL*Verilog System. VHDL Compiler. User's Manual, Version 4 VHDL*Verilog System. LEDA Procedural Interface (LPI) Implementor's Guide, Version 4 Synthesis of Decision Diagrams from Clock-Driven Multi-Process VHDL Descriptions for Test Generation Writing High Performance VHDL Models Hierarchical Compiled Event-Driven Logic Simulation Hybrid Techniques for Fast Functional Simulation VHDL Simulations ? Tips for Speeding Logic Verification Using Binary Decision Diagrams in a Logic Synthesis Environment Enhanced Visibility and Performance in Functional Verification by Reconstruction, th International Conference on Mixed Design of Integrated Circuits and Systems, £ odz Euro-VHDL'91 Conference IEEE International Conference on Computer-Aided Design ICCAD'89 Automation Conference DAC'98 IEEE International Conference on Computer-Aided Design ICCAD'88 Focus Report: Formal Verification, Cycle-Based Simulation, Timing Analysis, and ESL Entry IEEE/ACM Design Automation Conference DAC'98, pp.608-613, 1988.

M. Mastretti, M. Mastretti, M. Sturlesi, and S. Tomasello, Static Analysis of VHDL Code: Simulation Efficiency and Complexity, Euro- DAC'95 with Euro-VHDL'95 Conference VHDL International Users' Forum Conference Spring 1995 VIUF'95, pp.7-8, 1995.

P. M. Maurer-]-e and . Mccluskey, Optimization of the Parallel Technique for Compiled Unit-Delay Simulation Logic Design Principles with Emphasis on Testable Semicustom Circuits, IEEE International Conference on Computer-Aided Design ICCAD'90, pp.70-7390, 1986.

P. Mcgeer, K. Mcmillan, A. Saldanha, A. Sangiovanni-vincentelli, P. Scaglia-]-k et al., Fast Discrete Function Evaluation Using Decision Diagrams CTL Model Checking Symbolic Model Checking " , An Advanced Study Institute of the NATO Science Committee on Verification of Digital and Hybrid Systems, Antalya Turkey Introduction to Hardware Description Languages Implemented in the 80's: VHDL " , in Fundamentals and Standards in Hardware Description Languages, NATO ASI Series HDL Interoperability: A Compiler Technology Perspective " , VHDL International Users' Forum Conference Fall Fundamentals and Standards in Hardware Description Languages Binary Decision Diagrams and Applications for VLSI CAD, Series E: Applied Science NATO ASI Series, Series E: Applied Science ModelSim PE/PLUS VHDL, Verilog, and Mixed-HDL Simulation for PCs Running Windows 95 & Windows NT. User's Guide Theorem Proving " , An Advanced Study Institute of the NATO Science Committee on Verification of Digital and Hybrid Systems, pp.402-407, 1993.

]. A. Morawiec, VHDL Simulation Performance Evaluation, 1998.

A. Morawiec, VHDL Simulation Performance Evaluation, 1999.

A. Morawiec, The Use of Hardware Description Language VHDL in Design of Electronic Integrated Circuits on the Example of a Graphic Processor Design " -Master of Science degree dissertation, 1993.

A. Morawiec, Inventaire des outils de preuve formelle de circuits développés en Europe Test d'utilisabilité de deux d'entre eux sur un exemple d'origine industrielle, Diplôme des Études Approfondies de Microélectronique (DEA), 1996.

A. Morawiec, Inventaire des outils de preuve formelle de circuits développés en Europe, 1997.

A. Morawiec and T. Gore, Emerging Standards for IP Exchange, Intellectual Property Conference IP97, pp.374-387, 1997.

A. Morawiec and J. Mermet, Behavioral Abstraction of HDL Models for Simulation Performance, Asia -Pacific Conference on Chip Design Languages APChDL2000 at 16 th IFIP World Computer Congress, 2000.
URL : https://hal.archives-ouvertes.fr/hal-01399147

A. Morawiec and J. Mermet, European Formal Verification Tools for Model Correctness, Libraries, Component Modeling, and Quality Assurance LCM&QA'97, pp.181-192, 1997.
URL : https://hal.archives-ouvertes.fr/hal-01092351

A. Morawiec and J. Mermet, A Survey of Formal Hardware Verification Tools Developed in Europe, Asia -Pacific Conference on Hardware Description Languages APCHDL'97, 1997.

A. Morawiec and J. Mermet, Méthodes pour l'amélioration de la performance de simulation, Colloque CAO de Circuits Intégrés et Systèmes, pp.262-265, 1999.

A. Morawiec and J. Mermet, Techniques for Improving the HDL Simulation Performance, Forum on Design Languages FDL'99, pp.91-100, 1999.
URL : https://hal.archives-ouvertes.fr/hal-01396292

A. Morawiec, R. Ubar, and J. Raik, Cycle-based simulation algorithms for digital systems using high-level decision diagrams (poster paper), Proceedings of the conference on Design, automation and test in Europe , DATE '00, p.743, 2000.
DOI : 10.1145/343647.344127

R. Murgai, F. Hirose, and M. Fujita, Speeding up Look-up-Table Driven Logic Simulation, IFIP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration VLSI'99, pp.385-397, 1999.
DOI : 10.1007/978-0-387-35498-9_34

E. Naroska, Parallel VHDL simulation, Proceedings Design, Automation and Test in Europe, pp.159-163, 1998.
DOI : 10.1109/DATE.1998.655851

Z. Navabi, Optimizing RTL Simulation Performance. Methodology and Modeling. Utility Modeling, RASSP-Sanders Project: Simulation Acceleration

Z. Navabi and A. Peymandoust, Optimizing RTL Simulation Performance by Reducing Simulation Activities, RASSP-Sanders Project: Simulation Acceleration

A. Ottens, W. Van-hoogstraeten, and H. , A New Flexible VHDL Simulator, Euro- DAC'94 with Euro-VHDL'94 Conference, pp.604-609, 1994.

S. L. Pandey, K. R. Subramanian, and P. A. Wilsey, A semantic model of VHDL for validating rewriting algebras, Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies, pp.167-176, 1996.
DOI : 10.1109/EURMIC.1996.546379

B. Paulsen and O. Levia, Techniques for Writing High Performance and High Quality VHDL Models, Euro-DAC'92 with Euro-VHDL'92 Conference, 1992.

A. Pawlak, F. Bouchard, and P. Bakowski, Survey on VHDL Modeling Guidelines, Libraries, Component Modeling, and Quality Assurance LCM&QA'97, pp.117-128, 1997.

D. Perrin, Finite Automata Handbook of Theoretical Computer Science Formal Models and Semantics, J. van Leeuwen, pp.1-58, 1990.

G. Peterson, Performance Tradeoffs for Emulation, Hardware Acceleration, and Simulation, International HDL Conference HDLCon, pp.222-229, 2000.
DOI : 10.1007/978-1-4757-3281-8_22

A. Peymandoust and Z. Navabi, VHDL Concurrent Simulation of RT Level Components, RASSP-Sanders Project: Simulation Acceleration

A. Peymandoust and Z. Navabi, VHDL Concurrent Simulation of RT Level Components " , VHDL International Users' Forum Conference Fall, pp.353-357, 1996.

A. Postula, VHDL Specific Issues in High Level Synthesis VHDL for Simulation, Synthesis and Formal Proofs of Hardware, pp.117-134, 1992.

R. Raghavan, J. P. Hayes, and W. R. Martin, Logic simulation on vector processors, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers, pp.268-271, 1988.
DOI : 10.1109/ICCAD.1988.122508

J. Raik and R. Ubar, High-level path activation technique to speed up sequential circuit test generation, European Test Workshop 1999 (Cat. No.PR00390), 1999.
DOI : 10.1109/ETW.1999.804289

J. Raik and R. Ubar, Sequential Circuit Test Generation Using Decision Diagram Models, IEEE Conference on Design, Automation and Test in Europe DATE'99, pp.736-740, 1999.

E. Röhm, Latest benchmark results of VHDL simulation systems, Proceedings of EURO-DAC. European Design Automation Conference, pp.406-411, 1995.
DOI : 10.1109/EURDAC.1995.527437

W. J. Schilp and P. Maurer, Unit delay simulation with the inversion algorithm, Proceedings of International Conference on Computer Aided Design, pp.412-417, 1995.
DOI : 10.1109/ICCAD.1996.569831

S. Schmerler, Y. Tanurhan, and K. D. Müller-glaser, Advanced optimistic approaches in logic simulation, Proceedings Design, Automation and Test in Europe, pp.362-368, 1998.
DOI : 10.1109/DATE.1998.655883

S. E. Schulz, A Tutorial Introduction to VITAL, Mentor Users' Group Conference, 1995.

C. Seger, An Introduction to Formal Hardware Verification, 1992.

E. M. Sentovich, A brief study of BDD package performance, International Conference on Formal Methods in Computer Aided Design Lecture Notes in Computer Science, issue.1166, pp.389-403, 1996.
DOI : 10.1007/BFb0031823

E. J. Shriver and K. A. Sakallah, Ravel: assinged-delay compiled-code logic simulation, IEEE/ACM International Conference on Computer-Aided Design, pp.364-368, 1992.
DOI : 10.1109/ICCAD.1992.279346

A. Silburt, A. Evans, G. Vrckovnik, M. Dufresne, and T. Brown, Functional Verification of ASICs in Silicon-Intensive Systems, DesignCon98 Conference, 1998.

A. Silburt, I. Perryman, J. Bergeron, S. Nichols, M. Dufresne et al., Accelerating concurrent hardware design with behavioural modelling and system simulation, Proceedings of the 32nd ACM/IEEE conference on Design automation conference , DAC '95, pp.528-533, 1995.
DOI : 10.1145/217474.217582

P. Sinander, VHDL Modelling Guidelines, European Space Agency ESA, 1994.

P. Sinander and S. Habinc, Using VHDL for Board Level Simulation, IEEE Design & Test of Computers, 1996.

S. P. Smith and . Larson, A High Performance VHDL Simulator With Integrated Switch and Primitive Modeling, Computer Hardware Description Languages and Their Applications IFIP, pp.299-313, 1990.

A. Srinivasan, T. Kam, S. Malik, and R. K. Brayton, Algorithms for discrete function manipulation, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, pp.92-95, 1990.
DOI : 10.1109/ICCAD.1990.129849

A. Stanculescu, HDL-Driven Digital Simulation, Fundamentals and Standards in Hardware Description Languages, NATO ASI Series, Series E: Applied Science, pp.263-280, 1993.
DOI : 10.1007/978-94-011-1914-6_8

J. Staunstrup, A Formal Approach to Hardware Design, 1994.
DOI : 10.1007/978-1-4615-2764-0

V. Stavridou, Formal Methods in Circuit Design, 1993.

N. S. Stollon and J. D. Provence, Measures of syntactic complexity for modeling behavioral VHDL, Proceedings of the 32nd ACM/IEEE conference on Design automation conference , DAC '95, pp.684-689, 1995.
DOI : 10.1145/217474.217611

. Synopsys, Cyclone VHDL Datasheet " , www.synopsys.com/products/simulation/ cyclone_ds.htm, 1999.

S. Switzer, D. Landoll, and T. Anderson, Functional Verification with Embedded Checkers, International HDL Conference HDLCon, pp.174-178, 2000.
DOI : 10.1007/978-1-4757-3281-8_7

S. A. Szygenda, Digital Systems Simulation. Digital Logic Simulation In a Time-Based, Table-Driven Environment. Part 1. Design Verification, Computer, pp.23-36, 1975.

K. Thirunarayan and R. Ewing, Characterizing a portable subset of behavioral VHDL-93, IFIP TC10 WG10.5 International Conference on Computer Hardware Description Languages and their Applications, pp.97-113, 1997.
DOI : 10.1007/978-0-387-35064-6_13

D. E. Thomas and P. R. Moorby, The Verilog Hardware Description Language, 1995.

W. Thomas, Automata on Infinite Objects Handbook of Theoretical Computer Science Formal Models and Semantics, pp.133-164, 1990.

B. Tuck, After Hard Knocks, Cycle-Based Simulators Stand Their Ground, ASIC & Tool Review, pp.76-80, 1996.

R. Ubar, Multi-Valued Simulation of Digital Circuits with Structurally Synthesized Binary Decision Diagrams, OPA (Overseas Publishers Association) N.V. Gordon and Breach Publishers, Multiple Valued Logic, pp.141-157, 1998.

R. Ubar, Vektorielle Alternative Graphen und Fehlerdiagnose für digitale Systeme, Nachrichtentechnik/Elektronik, issue.311, pp.25-29, 1981.

R. Ubar, Test synthesis with alternative graphs, IEEE Design & Test of Computers, vol.13, issue.1, pp.48-59, 1996.
DOI : 10.1109/54.485782

R. Ubar, A. Morawiec, and J. Raik, Cycle-based Simulation with Decision Diagrams, IEEE Conference on Design, Automation and Test in Europe DATE'99, pp.454-458, 1999.
URL : https://hal.archives-ouvertes.fr/hal-01396462

R. Ubar, A. Morawiec, and J. Raik, Vector Decision Diagrams for Simulation of Digital Systems, Design and Diagnostics of Electronic Circuits and Systems Workshop DDECS2000, pp.44-51, 2000.
URL : https://hal.archives-ouvertes.fr/hal-01396444

R. Ubar, A. Morawiec, and J. Raik, Back-tracing and event-driven techniques in high-level simulation with decision diagrams, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2000.
DOI : 10.1109/ISCAS.2000.857064

URL : https://hal.archives-ouvertes.fr/hal-01396437

R. Ubar, J. Raik, and A. Morawiec, High-Level Decision Diagrams for Improving Simulation Performance of Digital Systems The 4 th World Multiconference on Systemics, Cybernetics and Informatics SCI', 2000.

C. A. Van-eijk, Formal Methods for the Verification of Digital Circuits The Netherlands, 1997.

J. Varghese, M. Butts, and J. Batcheller, An efficient logic emulation system, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.1, issue.2, pp.171-174, 1993.
DOI : 10.1109/92.238418

I. Veribest, VeriBest Online Documentation. VB98.0, VeriBest Incorporated, 1998.

E. Villar and P. Sanchez, Synthesis applications of VHDL, Fundamentals and Standards in Hardware Description Languages, NATO ASI Series, Series E: Applied Science, pp.231-262, 1993.
DOI : 10.1007/978-94-011-1914-6_7

A. P. Voss, R. H. Klenke, and J. H. Aylor, The Analysis of Modeling Styles for System Level VHDL Simulations " , VHDL International Users' Forum Conference Fall, 1995.

Z. Wang and P. Maurer, LECSIM: a levelized event-driven compiled logic simulator, 27th ACM/IEEE Design Automation Conference, pp.491-496, 1990.
DOI : 10.1109/DAC.1990.114905

J. A. Wicks and J. R. Armstrong, Rating the Efficiency of VHDL Behavioral Models " , VHDL International Users' Forum Conference Fall, pp.345-351, 1996.

J. A. Wicks, J. R. Armstrong, and R. James, VHDL Model Efficiency, Asian-Pacific Conference on Hardware Description Languages APCHDL'96, pp.150-154, 1996.

J. Willis, Z. Li, and T. Lin, Use of embedded scheduling to compile VHDL for effective parallel simulation, Proceedings of EURO-DAC. European Design Automation Conference, pp.400-405, 1995.
DOI : 10.1109/EURDAC.1995.527436

J. Willis and R. Newshutz, Auriga: A Compiler that Addresses NUMA Architectures, 1996.

J. Willis and D. Siewiorek, Optimizing VHDL compilation for parallel simulation, IEEE Design & Test of Computers, vol.9, issue.3, 1992.
DOI : 10.1109/54.156157

P. A. Wilsey, Developing a Formal Semantic Definition of VHDL " , in VHDL for Simulation, Synthesis and Formal Proofs of Hardware, J. Mermet, pp.245-256, 1992.

P. A. Wilsey, D. M. Benz, and S. L. Pandey, A model of VHDL for the analysis, transformation, and optimization of digital system designs, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair, pp.611-616, 1995.
DOI : 10.1109/ASPDAC.1995.486377

P. A. Wilsey, S. L. Pandey, and K. Umamageswaran, A Formal Model of Digital Systems Compatible with VHDL, RASSP Digest, vol.3, pp.46-48, 1996.

S. Woods and G. Casinovi, Gate-level simulation of digital circuits using multi-valued Boolean algebras, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), pp.413-419, 1995.
DOI : 10.1109/ICCAD.1995.480149

J. Yuan, J. Shen, J. Abraham, and A. Aziz, On combining formal and informal verification, Conference on Computer-Aided Verification CAV'97, 1997.
DOI : 10.1007/3-540-63166-6_37

A. Zamfirescu, Logic and Arithmetic in Hardware Description Languages-108 SELMUXX <= '1'; SELMUXY <= '1'; WRITEX <= '1'; WRITEY <=, Fundamentals and Standards in Hardware Description Languages, NATO ASI Series, Series E: Applied Science, p.79, 1993.