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Amélioration de performance de la simulation des modèles décrits en langages de description de matériel

Abstract : The growing complexity of electronic systems stimulated by IC's technology progress demands a corresponding growth of the productivity of design and verification methods. The low performance of simulation is one of the obstacles preventing a delivery of high quality products in a short time and at a low cost. In this thesis we propose methods aimed at improving the simulation performance of event-driven and cycle-based simulation techniques of HDL models. Automated optimization and transformation methods of VHDL models, developed to accelerate the event-driven simulation are presented first. These methods, based on the precise measure of simulation performance of VHDL language constructs, convert an initial VHDL model into another functionally equivalent VHDL model offering a better simulation performance. Other acceleration techniques, denoted as abstraction methods, focus on removing from a model all irrelevant details of its behavior or structure. We propose three such methods: behavioral abstraction, data-type abstraction and object abstraction. Prototype tools compatible with currently used simulators are developed to support automatic application of these methods. For the purpose of improving of the cycle-based simulation efficiency a representation of a digital system by high-level decision diagrams (DDs) is introduced. Some forms of DDs: vector decision diagrams, compressed or not (VDDs and CVDDs) and register-oriented DDs are developed to optimize
the representation of a system at different levels of abstraction. In addition, new simulation algorithms of a network of DDs are proposed to further accelerate the simulation execution. These algorithms implement
separately or in combination two simulation techniques: the event-driven and back-tracing techniques. The prototype tools are build, based on the DDs simulator, which allow to efficiently simulate various types of decision diagrams with appropriate simulation algorithms
keyword : VHDL
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Submitted on : Wednesday, June 11, 2003 - 3:44:37 PM
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  • HAL Id : tel-00002983, version 1




A. Morawiec. Amélioration de performance de la simulation des modèles décrits en langages de description de matériel. Micro et nanotechnologies/Microélectronique. Université Joseph-Fourier - Grenoble I, 2000. Français. ⟨tel-00002983⟩



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