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Conception pour la faible consommation en technologies SOI 2D et 3D : application à l'arithmétique

Abstract : This work discussed first with the causes of energy dissipation in integrated circuits and presented the performances metrics associated with this dissipation. Then were described the technologies that were used; these are the two dimensional and three dimensional T gate 100nm SOI technologies. The three dimensional technology consists in two layers of transistors where the P-channel devices are integrated on top of the N-channel ones. Design methodologies and standard-cell libraries were developed. Finally, low energy combinatorial arithmetic operators architectures were evaluated, modelled and implemented in these technologies. The target operations were addition, multiplication and division.
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https://tel.archives-ouvertes.fr/tel-00002982
Contributor : Lucie Torella <>
Submitted on : Wednesday, June 11, 2003 - 3:23:12 PM
Last modification on : Friday, December 11, 2020 - 8:28:03 AM
Long-term archiving on: : Friday, April 2, 2010 - 6:45:24 PM

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  • HAL Id : tel-00002982, version 1

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S.J. Abou-Samra. Conception pour la faible consommation en technologies SOI 2D et 3D : application à l'arithmétique. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 1998. Français. ⟨tel-00002982⟩

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