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Une méthodologie de conceptionde circuits intégrés quasi-insensibles aux délais :application à l'étude et à la réalisation d'un processeur RISC 16-bit asynchrone

Abstract : Unlike synchronous circuits, asynchronous circuits are not sequenced using a global clock signal. These circuits are locally synchronized using an adapted signaling and a local communication mechanism. Thus, asynchronous circuits offer interesting perspectives for system integration in deep submicron technologies such as : robustness, low noise, low power, good modularity. Nevertheless, the lack of associated design methodologies and tools prevent them from being widely spread. This thesis first specifies a design methodology for quasi-delay insensitive asynchronous circuits. Quasi delay insensitive circuits are the most robust asynchronous circuits, which is a major advantage for upcoming technologies. The proposed design methodology allows to model circuits using a high level language, to simulate them in a standard environment, and to generate circuits using only standard cells. This methodology was then applied to the study and design of a 16-bit RISC processor. Its original architecture enables in-order issue of instructions and out-of-order completion of their execution. It is shown that the asynchronous execution mode can weaken synchronizations, leading to the implementation of units exhibiting minimal execution-time and power-consumption. The prototype fabricated with the 0.25um CMOS technology from STMicroelectronics, is one of the fastest asynchronous processor designed so far.
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https://tel.archives-ouvertes.fr/tel-00002974
Contributor : Lucie Torella <>
Submitted on : Wednesday, June 11, 2003 - 10:22:14 AM
Last modification on : Friday, December 11, 2020 - 8:28:03 AM
Long-term archiving on: : Friday, April 2, 2010 - 7:14:04 PM

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  • HAL Id : tel-00002974, version 1

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Pascal Vivet. Une méthodologie de conceptionde circuits intégrés quasi-insensibles aux délais :application à l'étude et à la réalisation d'un processeur RISC 16-bit asynchrone. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2001. Français. ⟨tel-00002974⟩

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