Single-event effects in avionics, IEEE Transactions on Nuclear Science, vol.43, issue.2, pp.461-474, 1996. ,
DOI : 10.1109/23.490893
Singe Event Effect Testing of the Intel 80368 Family and 80486 Microprocessor, Proceeding of Second European Conference on Radiation and its Effects on Component and Systems (RADECS'95), pp.263-269, 1995. ,
Ionizing Radiation Effects in MOS Devices and Circuits, 1989. ,
Single event upsets in space, 21st Aerospace Sciences Meeting, 1983. ,
DOI : 10.2514/6.1983-164
Heavy Ion-Induced Single Event Upsets of Microcircuits; A Summary of the Aerospace Corporation Test Data, IEEE Transactions on Nuclear Science, vol.31, issue.6, 1984. ,
DOI : 10.1109/TNS.1984.4333481
Single event upsets in space, 21st Aerospace Sciences Meeting, 1983. ,
DOI : 10.2514/6.1983-164
A Summary of JPL Single Event Upset Test Data from May 1982, Through January 1984, IEEE Transactions on Nuclear Science, vol.31, issue.6, p.1186, 1985. ,
DOI : 10.1109/TNS.1984.4333480
Pulsed laser validation of recovery mechanisms of critical SEE's in an artificial neural network system, RADECS 97. Fourth European Conference on Radiation and its Effects on Components and Systems (Cat. No.97TH8294), pp.110-111, 1997. ,
DOI : 10.1109/RADECS.1997.698934
Single Event Effect Testing of the Intel 80368 Family and the 80468 Microprocessor, Proceeding. of Second Fourth European Conference on Radiation and its Effects on Component and Systems (RADECS'95), pp.263-269, 1995. ,
Radiaion Hardening Technics Facing Total Dose, SEU and SEL in the space Environment, 1993. ,
Effectiveness and limitations of various software techniques for "soft error" detection: a comparative study, Proceedings Seventh International On-Line Testing Workshop, 2001. ,
DOI : 10.1109/OLT.2001.937838
URL : https://hal.archives-ouvertes.fr/hal-00008210
Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits, IEEE Transactions on Nuclear Science, vol.41, issue.6, pp.41-2229, 1994. ,
DOI : 10.1109/23.340567
An SEU-hardened CMOS data latch design, IEEE Transactions on Nuclear Science, vol.35, issue.6, 1988. ,
DOI : 10.1109/23.25522
Low power SEU immune CMOS memory circuits, IEEE Transactions on Nuclear Science, vol.39, issue.6, pp.1679-1684, 1992. ,
DOI : 10.1109/23.211353
Time redundancy based soft-error tolerance to rescue nanometer technologies, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), pp.86-94, 1999. ,
DOI : 10.1109/VTEST.1999.766651
URL : https://hal.archives-ouvertes.fr/hal-00013764
Software Fault Tolerant Techniques from a Real-Time System Point of View, 1998. ,
Algorithm-Based Fault Tolerance for Matrix Operations, IEEE Trans. on Computers, vol.33, pp.518-528, 1984. ,
Design and evaluation of system-level checks for on-line control flow error detection, IEEE Transactions on Parallel and Distributed Systems, vol.10, issue.6, pp.627-641, 1999. ,
DOI : 10.1109/71.774911
Concurrent error detection using watchdog processors-a survey, IEEE Transactions on Computers, vol.37, issue.2, pp.160-174, 1998. ,
DOI : 10.1109/12.2145
Concurrent process monitoring with no reference signatures, IEEE Transactions on Computers, vol.43, issue.4, pp.475-480, 1994. ,
DOI : 10.1109/12.278485
Use of Tune and Address Signatures for Control Flow Checking, th IFIP Working Conference on Dependable Computing for Critical Appleation (DCCA-5), pp.113-124, 1995. ,
An Approach to Concurrent Control Flow Checking, IEEE Transactions on Software Engineering, vol.6, issue.2, pp.126-137, 1980. ,
DOI : 10.1109/TSE.1980.234478
Design of microprocessors with built-in on-line test, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium, pp.450-456, 1990. ,
DOI : 10.1109/FTCS.1990.89381
URL : https://hal.archives-ouvertes.fr/hal-00015260
Experimental Evaluation of Two Concurrent Error Detection Schemes, 16 th International Symposium on Fault Tolerant Computing (FTCS-16), pp.138-143, 1986. ,
Continuous signature monitoring: low-cost concurrent detection of processor control errors, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.9, issue.6, pp.629-641, 1990. ,
DOI : 10.1109/43.55193
A new approach to control flow checking without program modification, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium, pp.334-341, 1991. ,
DOI : 10.1109/FTCS.1991.146682
URL : https://hal.archives-ouvertes.fr/hal-00015242
Control-flow checking via regular expressions, Proceedings 10th Asian Test Symposium ,
DOI : 10.1109/ATS.2001.990300
URL : http://porto.polito.it/1416288/1/2001_ATS_ControlFlow.pdf
A Program Structure for Error Detection and Recovery, Lecture Notes in Computer Science, vol.16, pp.172-187, 1974. ,
System Structure for Software Fault Tolerant, IEEE Trans. On Software Engineering, vol.1, issue.2, pp.220-232, 1975. ,
Fault-Tolerant Software for Real-Time Applications, ACM Computing Surveys, vol.8, issue.4, pp.391-407, 1967. ,
DOI : 10.1145/356678.356681
On the Implementation Of N-Version Programming for Software Fault Tolerant During Program Execution, Proceedings of 1977 International Conference on Computer Software and Application, pp.149-155, 1977. ,
Soft-error detection through software fault-tolerance techniques, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99), pp.210-218, 1999. ,
DOI : 10.1109/DFTVS.1999.802887
Hardening the software with respect to transient errors: a method and experimental results, 2000. ,
URL : https://hal.archives-ouvertes.fr/hal-01384224
System safety through automatic high-level code transformations: an experimental evaluation, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001. ,
DOI : 10.1109/DATE.2001.915040
URL : https://hal.archives-ouvertes.fr/hal-00008218
Handbook of Radiation Effects, 1993. ,
Prediction du Taux d'erreurs d'Architectures Digitale: Une Méthode et Résultats experimentaux, 2000. ,
THESIC: A testbed suitable for the qualification of integrated circuits devoted to operate in harsh environment, IEEE European Test Workshop, pp.27-29, 1998. ,
URL : https://hal.archives-ouvertes.fr/hal-01384973
An automated technique to provide software applications with SEU detection capabilities: basic principles and preliminary results A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks Error detection and correction by software means: a new method and preliminary experimental results Radiation and its effects on Components and Systems Coping with SEUs/SETs in Microprocessors by means of Low-Cost Solutions: A comparative study and Experimental results Effectiveness and limitations of various software techniques for "soft error " detection: A comparative study System safety through automatic high-level code transformations: an experimental evaluation Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors, WE DSP32C Digital Signal Processor. Information Manual 15th Symposium On Integrated Circuits And System Design 7th IEEE International On-Line Testing Workshop Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante Robustness of Neural Network in Radioactive Environment 8th International Conference on Microelectronics for Neural, Fuzzy and Bio-inspired Systems, 1998. ,
Evaluating the effectiveness of a software fault-tolerance technique on RISC and CISCbased architectures, 6th IEEE International On-Line Testing Workshop Mallorca, Spain, 2000. ,
URL : https://hal.archives-ouvertes.fr/hal-00008226
Hardening the software with respect to transient errors: a method and experimental results, 2000. ,
URL : https://hal.archives-ouvertes.fr/hal-01384224