]. F. Bibliographie-[-anc86 and . Anceau, The Architecture of Microprocessors, 1986.

]. P. Bacq97 and . Bacquet, Translating SDL into OPNET: From formal validation to performance evaluation, dans Proc. of OPNETWORK Conference, 1997.

]. R. Berg95 and . Bergamaschi, Productivity Issues in High-Level Design: Are Tools Solving the Real Problems?, Proc. 32 rd Design Automation Conference, 1995.

]. R. Bray87 and . Brayton, MIS: a Multiple Level Logic Optimization System, IEEE Trans. CAD, issue.6, pp.1062-1081, 1987.

]. R. Cam91 and . Camposano, Path-based Scheduling for Synthesis, IEEE Trans. On CAD, vol.10, issue.1, pp.85-93, 1991.

]. R. Cam96 and . Camposano, Behavioral Synthesis, Proc. 33 rd Design Automation Conference, 1996.

]. R. Camp87 and . Camposano, Structurel Synthesis in the Yorktown Silicon Compiler, 1987.

D. [. Chaiyakul, L. Gajski, and . Ramachandran, High-level transformations for minimizing syntactic variances, Proceedings of the 30th international on Design automation conference , DAC '93, 1993.
DOI : 10.1145/157485.164956

]. A. Daka96, R. Dasgupta, and . Karri, Electromigration Reliability Enhancement via Bus Activity Distribution, Proc. 33 rd Design Automation Conference, 1996.

]. C. Dave97, P. Dangelo, and . Verhofstadt, Report of the Ad Hoc Working Group on Design & Test MUSTANG: State Assignment for Finite State Machines for Multi-Level Logic Implementations, Published on the Internet Proc. ICCAD, pp.16-19, 1987.

[. Eikerling, W. Hardt, J. Gerlach, and E. W. , A methodology for rapid analysis and optimization of embedded systems, Proceedings IEEE Symposium and Workshop on Engineering of Computer-Based Systems, 1996.
DOI : 10.1109/ECBS.1996.494536

]. C. Ewer90 and . Ewering, Automatic High Level Synthesis of Partitioned Busses, Proceedings of the IEEE International Conference on Computer-Aided Design, pp.304-307, 1990.

]. O. Faeo94, A. Faergemand, and . Olsen, Introduction to SDL-92, Computer Networks and ISDN Systems, vol.26, pp.1143-1167, 1994.

]. J. Fis81 and . Fisher, Trace Scheduling: A Technique for Global Microcode Compaction, IEEE Trans. on Computers, issue.7, pp.30-478, 1981.

]. M. Freta87, R. E. Fredman, and . Tarjan, Fibonacci Heaps and Their Uses in Improved Network Optimization Algorithms, Journal of the ACM, vol.34, pp.596-615, 1987.

]. D. Gaj92, N. Gajski, A. Dutt, E. Y. Wu, and . Lin, High-Level Synthesis: Introduction to Chip and System Design, 1992.

D. D. Gajski, F. Vahid, S. Narayan, and E. J. Gong, Specification and Design of Embedded Systems, 1994.

]. E. Gikn84, &. J. Girczyc, and . Knight, An ADA to standard cell hardware compiler based on graph grammars and scheduling, Proc. of ICCD, 1984.

]. L. Gprab98, M. Guerra, J. Potkonjak, and . Rabaey, A Methodology for Guided Behavioral-Level Optimization, Design Automation Conference, pp.309-314, 1998.

]. R. Gumi90, G. Gupta, and . De-micheli, Partitioning of Functional Models of Synchronous Digital Systems, IEEE Int. Conference on Computer Aided Design, 1990.

F. [. Gajski, S. Vahid, J. Narayan, and . Gong, System-level exploration with SpecSyn, Proceedings of the 35th annual conference on Design automation conference , DAC '98, p.812, 1998.
DOI : 10.1145/277044.277252

J. Henkel and R. Ernst, A Path-Based Estimation Technique for Estimating Hardware Runtime in HW/SW-Cosynthesis, Proceedings 8th IEEE International Symposium on System Level Synthesis, pp.116-121, 1995.

P. [. Hessel, C. A. Marrec, M. Valderrama, A. A. Romdhani, and . Jerraya, MCI ??? Multilanguage Distributed Co-Simulation Tool, DIPES 98, 1998.
DOI : 10.1007/978-0-387-35570-2_17

URL : https://hal.archives-ouvertes.fr/hal-00016267

]. C. Hsu90, Y. S. Huang, Y. L. Chen, Y. C. Lin, and . Hsu, Data Path Allocation Based on Bipartite Weighted Matching, Proc. 27 th Design Automation Conference, 1990.

]. T. Hu61 and . Hu, Parallel Sequencing and Assembly Line Problems, Operations Research, pp.841-848, 1961.

H. [. Jerraya, P. Ding, E. M. Kission, and . Rahmouni, Behavioral Synthesis and Component Reuse with VHDL, 1997.
DOI : 10.1007/978-1-4615-6315-0

]. A. Jeob94, K. Jerraya, and . O-'brien, SOLAR: An Intermediate Format for System-Level Modeling and Synthesis, 1994.

C. [. Küçükçakar, J. Chen, W. Gong, T. E. Philipsen, and . Tkacik, Matisse: an architectural design tool for commodity ICs, IEEE Design & Test of Computers, vol.15, issue.2, 1998.
DOI : 10.1109/54.679205

]. K. Keu94 and . Keutzer, The impact of CAD on the Design of Low Power Digital Circuits, IEEE Symposium on Low Power Electronics, pp.10-12, 1994.

P. Kission, «Exploitation de la Hiérarchie et de la Réutilisation de blocs par la Synthèse de Haut Niveau», Thèse de doctorat, 1996.

P. [. Kurdahi, C. Jha, E. N. Ramachandran, and . Dutt, Towards More Realistic Physical Design Models for High Level Synthesis, Workshop on Synthesis And System Integration of Mixed Technologies, 1993.

]. D. Kna96 and . Knapp, Behavioral Synthesis, 1996.

]. D. Knpar91, A. Knapp, and . Parker, The ADAM design planning engine, IEEE Trans. on Computer-Aided Design, vol.10, issue.7, pp.829-875, 1991.

]. S. Kroli98 and . Krolikoski, Considerations on the Usability of Behavioral Synthesis, Design, Automation and Test in Europe, 1998.

]. N. Kudu97, S. Dutt, F. Ohm, and . Kurdahi, A Unified Lower Bound Estimation Technique for High-Level Synthesis, IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 1997.

]. F. Kugaj93, D. D. Kurdahi, C. Gajski, V. Ramachandran, and . Chaiyakul, Linking Register-Transfer and Physical Levels of Design, IEICE Transactions on Information and Systems, 1993.

]. D. Kumic92, G. Ku, ]. K. De-michelikupa90, A. C. Küçükçakar, and . Parker, High-Level Synthesis of ASICs under Timing and Synchronization Constraints Data Path Tradeoffs using MABAL, Proceedings of the 28 th Design Automation Conference, pp.511-516, 1990.

]. A. Lapot98, G. D. Srinivasan, D. P. Huber, and . Lapotin, Accurate Area and Delay Estimation from RTL Descriptions, IEEE Trans. on VLSI systems, vol.6, issue.1, pp.168-172, 1998.

W. [. Ly, E. F. Elwood, and . Girczyc, A generalized interconnect model for data path synthesis, Conference proceedings on 27th ACM/IEEE design automation conference , DAC '90, pp.168-173, 1990.
DOI : 10.1145/123186.123248

]. J. Lhlin89, Y. C. Lee, Y. L. Hsu, and . Lin, A new Integer Linear Programming Formulation for the Scheduling Problem in Data Path Synthesis, Proc. of ICCAD, pp.20-23, 1989.

J. Li and R. K. Gupta, HDL optimization using timed decision tables, Proceedings of the 33rd annual conference on Design automation conference , DAC '96, 1996.
DOI : 10.1145/240518.240528

D. [. Ly, R. Knapp, D. Miller, and . Macmillen, Scheduling using behavioral templates, Proceedings of the 32nd ACM/IEEE conference on Design automation conference , DAC '95, pp.101-106, 1995.
DOI : 10.1145/217474.217514

P. [. Landwehr, E. R. Marwedel, and . Dömer, OSCAR: Optimum Simultaneous Scheduling, Allocation and Resource Binding Based on Integer Programming, Proc. of European Conference on Design Automation, 1994.

J. [. Lippens, A. Van-meerbergen, W. Van-der-werf, B. Verhaegh, J. Mcsweeney et al., PHIDEO: a silicon compiler for high speed algorithms, Proceedings of the European Conference on Design Automation., 1991.
DOI : 10.1109/EDAC.1991.206442

]. G. Mar98 and . Marchioro, «Découpage Transformationnel pour la Conception des Systèmes Mixtes Logiciel, 1998.

]. M. Mcfa90, A. C. Mcfarland, R. Parker, and . Camposano, The High-Level Synthesis of Digital Systems, Proceedings of the IEEE, vol.78, issue.2, pp.301-317, 1990.

]. M. Mcfar86 and . Mcfarland, Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral specifications, Proc. 23 rd Design Automation Conference, pp.474-480, 1986.

J. [. Marchioro, A. A. Daveau, and . Jerraya, Transformational partitioning for co-design of multiprocessor systems, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97, pp.508-515, 1997.
DOI : 10.1109/ICCAD.1997.643585

URL : https://hal.archives-ouvertes.fr/hal-00008111

]. K. Mehnä99, . Mehlhorn, . St, and . Näher, The LEDA Platform of Combinatorial and Geometric Computing, 1999.

J. [. Madsen, P. V. Grode, M. E. Knudsen, A. Petersen, and . Haxthausen, LYCOS: the Lyngby Co-Synthesis System, Design Automation for Embedded Systems, vol.2, issue.2, pp.195-235, 1997.
DOI : 10.1023/A:1008884219274

]. C. Mobr92, F. Monahan, and . Brewer, Communication Driven Interconnect synthesis Workshop on High-Level Synthesis Concurrent Analysis Techniques for Data Path Timing Optimization, Proc. 6 th Int Proc. 33 rd Design Automation Conference, 1992.

M. Nemani and F. N. Najm, Delay Estimation of VLSI Circuits from a High-Level View, Proc. of the 35 th Design Automation Conference, 1998.

M. [. O-'brien, A. A. Rahmouni, and . Jerraya, DLS: A scheduling algorithm for high-level synthesis in VHDL, Proc. of the European Conference on Design Automation, 1993.

R. H. Otten and R. K. Brayton, Planning for Performance, Proc. 35 th Design Automation Conference, 1998.

]. P. Padu95, N. Panda, and . Dutt, 1995 High Level Synthesis Design Repository, International Symposium on System Synthesis, 1995.

]. P. Pakn89, J. P. Paulin, and . Knight, Force-Directed Scheduling for the Behavioral Scheduling of ASICs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.8, issue.6, 1989.

]. A. Park79 and . Parker, The CMU Design Automation System: An Example of Automated Data Path Design, Proc. of the 16 th Design Automation Conference, 1979.

]. I. Park92 and . Park, AMICAL : Un Assistant pour la Synthèse et l'Exploration Architecturale des Circuits de Commande, Thèse de Doctorat, TIM3 ? Institut National Polytechnique de Grenoble, 1992.

]. C. Rakur94, F. J. Ramachandran, and . Kurdahi, Incorporating the Controller effects during Register-Transfer Level Synthesis, Proc. of the European Design Automation Conference, 1994.

]. C. Rakur94b, F. J. Ramachandran, and . Kurdahi, Combined Topological and Functionality-Based Delay Estimation Using a Layout-Driven Approach for High-Level Applications, IEEE Trans. On CAD of Integrated Circuits and Systems, vol.13, issue.12, pp.1450-1460, 1994.

]. J. [-raman87, H. Rabaey, J. De-man, G. Vanhoof, F. Goossens et al., CATHEDRAL-II : A Synthesis System for Multiprocessor DSP Systems A Loop-based Scheduling Algorithm for Hardware Description Languages, Parallel Processing Letters, pp.351-364, 1987.

[. James, Object-Oriented Modeling and Design, 1991.

]. Q. Some92, Y. Ji, M. Oh, F. Lightner, and . Somenzi, Technology Independent Estimation of Area in Logic Synthesis, Proc. of Synthesis and Simulation Meeting and International Interchange (SASIMI), pp.171-180, 1992.

A. [. Suzuki and . Sangiovanni-vincentelli, Efficient Software Performance Estimation Methods for Hardware/Software Codesign, Proceeding of Design Automation Conference, 1996.
DOI : 10.1109/dac.1996.545647

]. H. Towi77, N. C. Torng, and . Wilhelm, The optimal interconnection of circuit modules in microprocessor and digital system design, IEEE Trans. on Computers, vol.26, issue.5, pp.450-495, 1977.

]. F. Tshsu92, Y. Tsai, and . Hsu, STAR: a system for hardware allocation in data path synthesis, IEEE Trans. CAD, pp.1053-1064, 1992.

]. C. Tssi86, D. P. Tseng, and . Siewiorek, Automated Synthesis of Data Path in Digital Systems, IEEE Trans. on Computer-Aided Design, vol.5, issue.3, pp.379-95, 1986.

]. F. Vagaj95, D. D. Vahid, and . Gajski, Incremental Hardware Estimation during Hardware/Software Functional Partitioning, IEEE Trans. on VLSI Systems, vol.3, issue.3, pp.459-461, 1995.

]. F. Vah95 and . Vahid, Procedure Exlining: A Transformation for Improved System and Behavioral Synthesis, International Symposium on System Synthesis, 1995.

J. Vanhoof, K. V. Rompaey, I. Bolsens, G. Goossens, and H. De-man, High-Level Synthesis for Real-time Digital Signal Processing, 1993.
DOI : 10.1007/978-1-4757-2222-2

]. R. Walc91, R. Walker, and . Camposano, A Survey of High-Level Synthesis Systems, 1991.

P. [. Cesário, P. Kission, A. A. Guillaume, and . Jerraya, Unified Evaluation Model for Interconnection Schemes Used in Behavioral Synthesis, International Workshop on Logic and Architectural Synthesis, 1997.

Z. [. Cesário, R. Sugar, A. A. Suescun, and . Jerraya, Overlap and Frontiers Between Behavioral and RTL Synthesis, Europe, 1999.

]. W. Woc99b, . Cesárioyeer95-]-w, R. Ye, and . Ernst, Environnement de Synthèse Flexible Worst Case Timing Estimation Based on Symbolic Execution, Colloque CAO de Circuits Intégrés et Systèmes, 1995.

]. T. Ywolf95, W. Yen, and . Wolf, Communication Synthesis for Distributed Embedded Systems, dans Proceedings of 1995 IEEE International Conference on Computer-Aided Design