T. Tast_components, tast_components.all; ENTITY MAIN IS PORT ( Resetb: in std_ulogic, LIBRARY

E. Main, O. Main_arch, . Main, . Signal, and . Gnd, std_ulogic:= '0'; SIGNAL VCC: std_ulogic:= '1'; SIGNAL Net_17 Net_21: std_ulogic; SIGNAL Net_22 Net_33: std_ulogic; SIGNAL Net_39, Net_26: std_ulogic; SIGNAL Net_27: std_ulogic; BEGIN Inst_Name_17: TAST_MULLER2 port map (Net_17

<. E_ack and . Net_39, C_ack <= Net_39, p.2

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