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Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques = methods and tools for multiprocessor systems on chip, hardware/software co-designExploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC

Abstract : Heterogeneous multiprocessor SoCs are becoming more and more required in order to accommodate the ever-increasing performance requirements of application domains such as xDSL, networking, wireless, and game applications. So in order to deal with these complex applications and to meet the more severe time-to-market constraints we need new system design methods.
Our aim in this work is to define a novel approach for the design of application-specific heterogeneous multiprocessor SoC. This approach must be based on a modular, flexible, and scalable architecture model allowing for the systematic design of application-specific multiprocessor SoC. Such a model is crucial to obtain an efficient design flow. Modularity is needed to master complexity. Flexibility is required to rapidly accommodate changes imposed by the environment. Scalability is required to handle a large class of applications at different scales. And last but not least, the systematic architecture design (i.e. automation) is required in order to shorten the design cycle.
The model we propose is made of a set of processors and IPs interacting through an on chip communication network. The components of our model may incorporate any kind of CPU (including DSP cores or MCUs) it may also contain hardware blocks, memories or any external pre-designed block. The communication network may be of whatever complexity; it can scale from a single bus to a network with complex structures (crossbar, switch network, hierarchical buses). A key point of this architecture model is the use of a generic wrapper model to adapt component interfaces to the on chip communication network. They act as communication coprocessors allowing to dissociate CPUs and IPs from the communication network. These communication interfaces may be designed through systematic assembling of few basic cells: we need one component adapter for each kind of CPU or IP and a channel adapter for each kind of protocol used. The communication protocols that can be used are not restricted to a specific model.
Our design flow follows the Y-chart where we use the application-specific parameters in order to configure an architecture platform and design the final SoC. The architecture design flow is associated with a flexible system validation. We chose to use a mixed-level cosimulation approach based on SystemC.
Several designs were achieved in order to illustrate and analyze the efficiency of the proposed architecture model and design flow. Three main applications were considered: a packet routing switch, IS-95 CDMA protocol, and the VDSL modem. The architecture platform that we used as an example consists of N processors (ARM7 and MC68000 processors). The communication network is a point-to-point network.
Finally, during this thesis, we also introduced a new methodology to rapidly explore the large design space encountered in hardware/software systems. The proposed methodology is based on a fast and accurate estimation approach. It has been implemented as an extension to a hardware/software codesign flow to enable the exploration of a large number of multiprocessor architecture solutions from the very start of the design process.
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https://tel.archives-ouvertes.fr/tel-00002932
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Submitted on : Tuesday, June 3, 2003 - 9:45:51 AM
Last modification on : Thursday, November 19, 2020 - 3:56:17 PM
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Amer Baghdadi. Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques = methods and tools for multiprocessor systems on chip, hardware/software co-designExploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC. Autre [cs.OH]. Institut National Polytechnique de Grenoble - INPG, 2002. Français. ⟨tel-00002932⟩

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