. Reenement, Permet de pr eciser qu'une relation d' equivalence aane une autre

M. Aagaard, R. B. Jones, C. , and H. Seger, Combining theorem proving and trajectory evaluation in an industrial environment, Proceedings of the 35th annual conference on Design automation conference , DAC '98
DOI : 10.1145/277044.277189

L. *. Arditi and . Bmd-can, *BMDs can delay the use of theorem proving for verifying arithmetic assembly instructions, Formal Methods in Computer-Aided Design (FMCAD'96), v olume 1166 of LNCS, pp.34-48, 1996.
DOI : 10.1007/BFb0031798

B. Barras, S. Boutin, C. Cornes, J. Courant, Y. Coscoy et al., The Coq P r oof Assistant Reference Manual: Version 6, 1997.

S. Ben-david, T. Heyman, O. Grumberg, and A. Schuster, Scalable distributed on-the--y symbolic model checking, Formal Methods in Computer-Aided design, pp.3-36, 1954.

V. Bertacco, M. Damiani, and S. Quer, Cycle-based symbolic simulation of gate-level synchronous circuits, Design Automation Conference

D. Borrione and P. Georgelin, Formal veriication of VHDL using VHDL-like A CL2 models, Proceedings of Forum on Design Languages (FDL'99), pages 105{116, 1999.

D. Borrione, P. Georgelin, and V. Rodrigues, Symbolic simulation and veriication of VHDL with ACL2, International Conference on HDL (HDLCONF'2000), pp.167-182, 2000.

D. Borrione, P. Georgelin, and V. Rodrigues, Using Macros to Mimic VHDL, Computer Aided R easoning: ACL2 Case Studies, pp.167-183, 2000.
DOI : 10.1007/978-1-4757-3188-0_11

URL : https://hal.archives-ouvertes.fr/hal-00016265

D. Borrione, J. Dushina, and L. Pierre, Formalization of nite state machines with data path for the veriication of high-level synthesis, XI Brazilian Symposium on Integrated Circuit Design (SBCCI'98), 1998.

D. Borrione and A. Salem, Denotational semantics of a synchronous VHDL subset, Formal Methods in System Design, pp.53-71, 1995.
DOI : 10.1007/BF01383873

URL : https://hal.archives-ouvertes.fr/hal-00014235

R. S. Boyer, D. Goldschlag, M. Kaufmann, and J. S. Moore, Functional instanciation in rst order logic, Artiical Intelligence and Mathematical Theory of Computation: Papers in Honor of John McCarthy, 1991.

R. S. Boyer and J. S. Moore, A Computational Logic, 1979.

S. Robert, J. Boyer, and . Strother-moore, Automated R easoning and Its Applications, c hapter Mechanized formal reasonning about programs and computing machines, 1996.

T. Peter, L. S. Breuer, C. Fernandez, and . Delgado-kloos, A Simple Denotational Semantics , Proof Theory and a Validation Condition Generator for Unit-Delay VHDL, Formal Methods in System Design, pp.27-51, 1995.

B. Brock, M. Kaufmann, and J. S. Moore, ACL2 theorems about commercial microprocessors, Formal Methods in Computer-Aided Design (FMCAD'96), pp.275-293, 1996.
DOI : 10.1007/BFb0031816

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

R. E. Bryant, Symbolic manipulation of boolean functions using a graphical representation, Proceedings of the 22nd ACM/IEEE Design Automation Conference, pp.688-694, 1985.

R. E. Bryant and Y. Chen, Veriication of Arithmetic Circuits with Binary Moment Diagrams, Proceedings of 32nd Design Automation Conference ( D AC'95), pages 535{541, 1995.

J. R. Burch and D. L. Dill, Automatic veriication of pipelined microprocessor control, Proceedings of International Conference on Computer-Aided V eriication, v olume LCNS 818, 1994.

A. J. Camilleri, A role for theorem proving in multi-processor design, Proceedings of CAV'98, pp.275-293, 1998.
DOI : 10.1007/BFb0028730

P. Camurati and P. Prinetto, Formal veriication of hardware correctness: Introduction and survey of current reseach, Computer (Journal), pp.9-19, 1988.

R. Chadha, Symbolic simulation: theory and application to protocol modeling and validation, Proceedings of ICNP, 1994 International Conference on Network Protocols
DOI : 10.1109/ICNP.1994.344369

E. Clarke, S. Jha, and D. Wang, Abstract BDDs: A Technique for Using Abstraction in Model Checking, Proceedings of Correct Hardware Design and Veriication Methods (CHARME'99), v olume 1703, 1999.
DOI : 10.1007/3-540-48153-2_14

E. M. Clarke, M. Khaira, and X. Zhao, Word Level Model Checking-Avoiding the Pentium FDIV Error, Proceedings of 33rd Design Automation Conference ( D AC'96), pages 645{648, 1996.

I. Corp, Fdiv replacement program information

I. Corp, Pentium iii processor speciication update

M. Cosnard and D. Trystram, Algorithmes et architectures paralleles Informatique intelligence artiicielle, 1993.

A. John, J. C. Darringer, and . King, Applications of symbolic execution to program testing, Computer, vol.11, issue.4, pp.51-60, 1978.

N. A. Day, J. R. Lewis, and B. Cook, Symbolic Simulation of Microprocessor Models Using Type Classes in Haskell, 1999.
DOI : 10.1007/3-540-48153-2_31

D. Deharbe, Veriication formelle de proprietes temporelles: etude et application au langage VHDL, 1996.

J. Dushina, V eriication Formelle des R esultats de la Synth ese de Haut Niveau, 1999.

P. Georgelin, Vhdl-acl2, see http, 2001.

M. J. Gordon and T. F. Melham, Introduction to HOLL A Theorem Proving Environment for Higher Order Logic, 1993.

D. Greve and M. Wilding, Two handy update-nth equality rules. Draft version -short note

D. Hardin, M. Wilding, and D. Greve, Transforming the theorem prover into a digital design tool: From concept car to off-road vehicle, Computer-Aided Veriication, CAV ' 9 8 , v olume 1427 of Lecture Notes in Computer Science, pp.39-44, 1998.
DOI : 10.1007/BFb0028729

M. Harrand, J. Sanchez, A. Bellon, J. Bulone, A. Tournier et al., A single-chip cif 30-hz, h261, h263, and h263+ video encoder/decoder with embedded display controller, IEEE Journal of solid-state circuits, N o v, 1999.

J. Harrison, Formal veriication of oating point trigonometric functions, Formal Methods in Computer-Aided Design, pp.217-233, 1954.

. Ieee-standards and . Board, IEEE Std 1076-1993 VHDL Language Reference Manual, 1993.

J. A. Darringer, The application of program veriication techniques to hardware veriication, Proceedings of the Sixteenth ACM/IEEE Design Automation Conference, pp.375-381, 1979.

M. Kaufmann, P. Manolios, and J. S. Moore, Computer Aided R easoning: An Approach, 2000.

M. Kaufmann and J. S. Moore, An industrial strength theorem prover for a logic based on Common Lisp, IEEE Transactions on Software E n g i n e ering, pp.203-213, 1997.
DOI : 10.1109/32.588534

M. Kaufmann and D. Russinoo, Veriication of pipeline circuits, ACL2 Workshop 2000 Procedings. U n i v ersity o f T exas at Austin, 2000.

M. Kaufmann and J. Strother-moore, ACL2: an industrial strength version of Nqthm, Proceedings of 11th Annual Conference on Computer Assurance. COMPASS '96, 1996.
DOI : 10.1109/CMPASS.1996.507872

K. Keutzer, The need for formal methods for integrated circuit design, Proceedings of FMCAD'96, pp.1-18, 1996.
DOI : 10.1007/BFb0031796

T. Lynch and M. Kaufmann, A mechanically checked proof of the correctness of the kernel of the amd5k86 oating-point division program, IEEE Transactions on Computers, p.47, 1998.

P. Manolios, Mu-Calculus Model-Checking, Computer Aided R easoning: ACL2 Case Studies, 2000.
DOI : 10.1007/978-1-4757-3188-0_7

P. Manolios, Veriication of pipelined machines in acl2, ACL2 Workshop 2000 Procedings. U n i v ersity o f T exas at Austin, 2000.

W. John, D. O-'leary-mark, T. F. Aagaard, and . Melham, Xs are for trajectory evaluation, booleans are for theorem proving (extended version)

I. Matt-kaufmann-computational and . Logic, The expander book, 1997.

K. C. Mcmillan, Symbolic Model Checking, Kluwer, 1993.

K. L. Mcmillan, Veriication of innnite state systems by compositional model checking, Proceedings of Correct Hardware Design and Veriication Methods (CHARME'99), v olume 1703, 1999.

J. S. Moore, Symbolic simulation: An ACL2 approach, FMCAD'98, pp.334-350, 1998.

J. Strother and M. , Rewriting for symbolic execution, 2000.

M. Olaf, T. Uller, and . Nipkow, Combining Model Checking and Deduction for I/O-Automata, 1995.

S. Narain, Reasoning about hybrid systems with symbolic simulation Reasoning about hybrid systems with symbolic simulation, Proceedings of 11th International Conference on Analysis and Optimization of Lecture Notes in Control and Information Sciences, 1994.

S. Narain, R. Chadha, S. Narain, and R. Chadha, Symbolic discrete-event simulation Symbolic Discrete-Event Simulation, Discrete-Event Systems, Manufacturing Systems and Communication Networks, LNCS BIBLIOGRAPHIE, vol.177, 1994.

F. Nicoli, Veriication formelle de descriptions VHDL comportementales, 1999.

S. Owre, J. M. Rushby, and N. Shankar, PVS: A prototype veriication system, 11th International Conference o n A utomated D e duction (CADE), v olume 607 of Lecture Notes in Artiicial Intelligence, pp.748-752, 1992.

L. Pierre, Induction-oriented veriication of replicated architectures described in vhdl, Journal of Circuits, Systems and Computers, vol.10, pp.3-4147, 2000.

S. Read and M. Edwards, A Formal Semantics of VHDL in Boyer-Moore Logic, Conference on Concurrent Engineering and EDA (CEEDA), P oole, Great Britain, 1994.

J. Reed, J. Sinclair, F. J. Guigand, J. E. Reed, F. Sinclair et al., Deductive reasoning versus model checking: two formal approaches for system development Deductive reasoning versus model checking: two formal approaches for system development, 1999.

G. Ritter, Sequential equivalence checking by s y m bolic simulation In Formal Methods in Computer-Aided Design FMCAD2000, v olume LNCS 1954, 2000.

G. Ritter, Formal Sequential Equivalence C h e cking of Digital Systems by Symbolic Simulation

D. Russinoo, A M e c hanically Checked Proof of IEEE Compliance of a Register-Transfer-Level Speciication of the AMD-K7 Floating-Point Multiplication, Division, and Square Root Instructions, Journal of Computation and Mathematics, vol.1, pp.148-200, 1998.

D. Russinoo, A case study in formal veriication of register-transfer logic with acl2: The oating point adder of the amd athlon processor, Formal Methods in Computer-Aided design, pp.3-36, 1954.

M. David and . Russinoo, A Formalization of a Subset of VHDL in the Boyer-Moore Logic, Formal Methods in System Design, pp.7-25, 1995.

S. Rajan, N. Shankar, and M. K. Srivas, An integration of model checking with automated proof checking, Proceedings of the 7th International Conference O n C o m puter Aided V eriication, v olume 939, pp.84-97, 1995.
DOI : 10.1007/3-540-60045-0_42

J. Sanchez, Speciication of IVT Reconstruction operator, F eb, 2000.

J. Sawada, Formal Veriication of an Advanced P i p elined Machine, 1999.

J. Sawada, J. Warren, and A. Hunt, Hardware Modeling Using Function Encapsulation, Formal Methods in Computer-Aided Design, 2000.
DOI : 10.1007/3-540-40922-X_15

K. Schneider and M. Huhn, Comparing model-checking and term-rewriting in the veriication of an embedded system, 1999.

N. Shankar, PVS: Combining specification, proof checking, and model checking, FMCAD'96, pp.257-264, 1996.
DOI : 10.1007/BFb0031813

G. L. Steele and J. , Common Lisp The Language, Second Edition Digital Press, 30 North Avenue, 1990.

D. G. Tatar, A P r ogrammer's Guide to Common Lisp, 1987.

P. Georgelin, V. Rodrigues, and D. Borrione, An acl2 model of vhdl for symbolic simulation and formal veriication. XIII Symposium on Integrated C i r cuits and Systems Design (SBCCI'00), 2000.

. Jr, . A. Warren, and . Hunt, The de language, Computer Aided R easoning: ACL2 Case Studies, 2000.

M. M. Wilding, D. A. Greve, and D. S. Hardin, EEcient simulation of formal processor models, 1998.

M. Matthew and . Wilding, Robust computer system proofs in pvs, LFM97: Fo u r t h N A S A L angley Formal Methods Workshop. NASA, NASA Conference Publication, 1997.

C. Wilson, D. L. Dill, and R. E. Bryant, Symbolic Simulation with Approximate Values, Formal Methods in Computer Aided Design FMCAD '2000, volume LNCS 1954, pp.486-504, 2000.
DOI : 10.1007/3-540-40922-X_29

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=