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Vérification formelle de systèmes digitaux synchrones, basée sur la simulation symbolique

Abstract : To satisfy market requirements, formal verification tools must allow designers to verify complex descriptions and reason about large or infinite sets of values. One should be able to concentrate on the correctness of algorithms and the essential mathematical properties of the blocks being designed. Most modern verification tools such as Model Checkers are restrictive because they can't deal with abstraction levels higher than Register Transfer Level, or similar Finite-State Machine models and are also limited on the total number of states. Theorem provers do not suffer from these restrictions, but they are not fully automated, and require methods to ease their systematic use in the standard design flow. This thesis addresses the formal verification of VHDL descriptions with the ACL2 theorem prover. We propose an environment combining symbolic simulation and theorem proving for the formal analysis of high level VHDL designs. Our approach consists in developping methods
- to formalize a synthesis subset of VHDL,
- to "direct" the theorem prover to perform symbolic simulation
- to use symbolic simulation results for proofs.
A tool was developped combining translators from VHDL to ACL2, symbolic simulation and proof engines in a user interface. The definitions and theorems that formalize the VHDL input are generated automatically, and the resulting model is executable. This same model is used for symbolic simulation and proof. By combining symbolic simulation and theorem proving, we aim at providing the verification engineer with a methodology to efficiently insert formal verification in the very early specification stages of a design. The theorem prover can be used to perform symbolic manipulations on the result expressions, and prove that they are equivalent to a specified function. The result of this thesis is to make theorem proving techniques more acceptable to a design team in terms of ease of use, and to notably decrease verification time in a design process.
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Contributor : Lucie Torella <>
Submitted on : Tuesday, June 3, 2003 - 10:17:04 AM
Last modification on : Friday, December 11, 2020 - 8:28:03 AM
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  • HAL Id : tel-00002931, version 1




P. Georgelin. Vérification formelle de systèmes digitaux synchrones, basée sur la simulation symbolique. Autre [cs.OH]. Université Joseph-Fourier - Grenoble I, 2001. Français. ⟨tel-00002931⟩



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