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Les limites technologiques du silicium et tolérance aux fautes

Abstract : Integrated circuit technology is approaching the ultimate limits of silicon in terms of geometry shrinking, power supply level, speed and density. By approaching these limits, circuits are becoming increasingly sensitive to any noise source (such as cross-talks, electromagnetic influence, noise on the power line, ground bounce) as well as radiative phenomena (e.g. alpha particles and atmospheric neutrons). Thus, the error rate due of the impact of ionizing particles (soft errors) or by the defects difficult to detect that may escape fabrication testing (e.g. timing faults) is drastically increased. In this thesis, we address these problems and we conclude that future integrated circuits have to be designed by using fault tolerance techniques, in order to maintain acceptable reliability levels. This analyze shows that logic parts are becoming as sensitive to soft errors as memories and therefore they need tobe protected. Traditional fault tolerance techniques (e.g. TMR, duplication) are of a high cost, they are not acceptable for low added value applications (for example commercial products). The temporal nature of the transient and timing faults is exploited in order to obtain efficient solutions by using self-checking structures as well as time redundancy techniques. These techniques decrease the hardware cost and have a small impact on the circuit performances. We have also developed a transient fault simulation methodology, which has allowed us to evaluate the efficiency of these methods with a very good accuracy.
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Contributor : Lucie Torella <>
Submitted on : Wednesday, May 28, 2003 - 4:17:05 PM
Last modification on : Tuesday, January 19, 2021 - 6:20:10 PM
Long-term archiving on: : Friday, April 2, 2010 - 7:10:15 PM


  • HAL Id : tel-00002907, version 1




Lorena Anghel. Les limites technologiques du silicium et tolérance aux fautes. Autre [cs.OH]. Institut National Polytechnique de Grenoble - INPG, 2001. Français. ⟨tel-00002907⟩



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