Self-Testing Analog Spiking Neuron Circuit

Abstract : Hardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35µm CMOS technology.
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Contributor : Haralampos Stratigopoulos <>
Submitted on : Tuesday, June 25, 2019 - 2:52:59 PM
Last modification on : Friday, July 5, 2019 - 3:26:03 PM


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  • HAL Id : hal-02164969, version 1


Sarah Ali El-Sayed, Luis Camuñas-Mesa, Bernabe Linares-Barranco, Haralampos-G. Stratigopoulos. Self-Testing Analog Spiking Neuron Circuit. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Jul 2019, Lausanne, Switzerland. ⟨hal-02164969⟩



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