282 articles – 2121 Notices  [english version]
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fulltext access Exploration des liens entre la synthèse de haut niveau (HLS) et la synthèse au niveau transferts de registres (RTL)
VIJAYARAGHAVAN V.
Institut National Polytechnique de Grenoble - INPG (29/12/1996), JERRAYA A. A. (Dir.) [tel-00010764 - version 1]
fulltext access Prototypage rapide d'architectures mixtes logiciels/matériels à partir de modèles mixtes C-VHDL
Changuel A.
Institut National Polytechnique de Grenoble - INPG (22/10/1996), Ahmed Amine Jerraya (Dir.) [tel-00345356 - version 1]
fulltext access Synthèse architecturale interactive et flexible
Ding H.
Institut National Polytechnique de Grenoble - INPG (1996-04-02), JERRAYA A. A. (Dir.) [tel-00010765 - version 1]
fulltext access Test et diagnostic de cartes et de MCMs partiellement boundary scan
TOUATI M. H.
Institut National Polytechnique de Grenoble - INPG (1996-01-24), COURTOIS B. (Dir.) [tel-00010767 - version 1]
fulltext access Synthèse au niveau système et conception de systèmes mixtes logiciels/matériels
BEN ISMAIL T.
Institut National Polytechnique de Grenoble - INPG (1996-01-09), JERRAYA A. A. (Dir.) [tel-00010766 - version 1]
A 2.5Gb/s ATM label translator implementation using high speed GaAs technology
Moussa I. et al
In Proceedings of ATM'96 Workshop - ATM'96 Workshop, United States (1996) [hal-00867817 - version 1]
A 2.5 Gb/s ATM label translator implemented by using GaAs technology
Moussa I. et al
ESSCIRC-'96.-Proceedings-of-the-22nd-European-Solid-State-Circuits-Conference., Suisse (1996) [hal-00082146 - version 1]
Proceedings on 2nd International On-Line Testing Workshop (IOLT'96), July 8-10, 1996, Biarritz - Saint-Jean-de-Luz, France
Nicolaidis M. et al
(1996) 265 pages [hal-00017275 - version 1]
International Workshop on Thermal Investigations of ICs and Microstructures (THERMINIC 1995) September 25-26, 1995, Grenoble, France: Special Issue, Sensors and Actuators A: Physical
Szekely V. et al
(1996) Issue 1 , 15 July, 1-70 [hal-00016713 - version 1]
Bare board test: From image processing to automatic test data generation
Benali A. et al
In Proceedings-of-the-Technical-Conference-IPC-Printed-Circuits-EXPO-'96 - Proceedings-of-the-Technical-Conference-IPC-Printed-Circuits-EXPO-'96, United States (1996) [hal-00016095 - version 1]
Analog/digital testing of loaded boards without dedicated test points
Vaucher C. et al
In Proceedings.-International-Test-Conference-1996.-Test-and-Design-Validity-IEEE-Cat.-No.96CH35976 - Proceedings.-International-Test-Conference-1996.-Test-and-Design-Validity-IEEE-Cat.-No.96CH35976, United States (1996) [hal-00016094 - version 1]
Modeling and control of an eddy current brake
Simeu E. et al
Control-Engineering-Practice Jan. 1996; 4(1): (1996) 19-26 [hal-00016042 - version 1]
Synthesis for dependability of finite state machines
Rochet R. et al
Technique et Science Informatiques (TSI) 15(4) (1996) 379-404 [hal-00015100 - version 1]
Standard and ROM-based synthesis of FSMs with control flow checking capabilities
Wending X. et al
In Proceedings.-14th-IEEE-VLSI-Test-Symposium-Cat.-No.96TB100043 - Proceedings.-14th-IEEE-VLSI-Test-Symposium-Cat.-No.96TB100043, United States (1996) [hal-00015089 - version 1]
ASYL-SdF: a synthesis tool for dependability in controllers
Rochet R. et al
IEICE Transactions on Information and Systems Oct. ; E79-D(10) (1996) 1382-8 [hal-00015087 - version 1]
ROM-based synthesis of fault-tolerant controllers
Wending X. et al
In Proceedings.-1996-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems-Cat.-No.96TB100081 - Proceedings.-1996-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems-Cat.-No.96TB100081, United States (1996) [hal-00015085 - version 1]
FPGA design migration: some remarks
Tchoumatchenko V. et al
In Field-Programmable-Logic.-Smart-Applications,-New-Paradigms-and-Compilers.-6th-International-Workshop-on-Field-Programmable-Logic-and-Applications,-FPL-'96-Proceedings. - Field-Programmable-Logic.-Smart-Applications,-New-Paradigms-and-Compilers.-6th-International-Workshop-on-Field-Programmable-Logic-and-Applications,-FPL-'96-Proceedings., Germany (1996) [hal-00014882 - version 1]
A low-power enable/disable GaAs MESFET differential logic
Ribas R.P. et al
In 18th-Annual-GaAs-IC-Symposium.-IEEE-Gallium-Arsenide-Integrated-Circuit-Symposium.-Technical-Digest-1996-Cat.-No.96CH35964 - 18th-Annual-GaAs-IC-Symposium.-IEEE-Gallium-Arsenide-Integrated-Circuit-Symposium.-Technical-Digest-1996-Cat.-No.96CH35964, United States (1996) [hal-00014793 - version 1]
A low-power differential cross-coupled FET logic for GaAs asynchronous design
Ribas R.P. et al
In GAAS-96.-European-Gallium-Arsenide-and-Related-III-V-Compounds-Applications-Symposium-and-Associated-CAD-Workshop. - GAAS-96.-European-Gallium-Arsenide-and-Related-III-V-Compounds-Applications-Symposium-and-Associated-CAD-Workshop., France (1996) [hal-00014780 - version 1]
A method for automatic design error location and correction in combinational logic circuits
Wahba A. et al
Journal-of-Electronic-Testing:-Theory-and-Applications April ; 8(2) (1996) 113-27 [hal-00014221 - version 1]