248 articles – 2008 Notices  [english version]
.:. Consultation > Liste par année > 1993 .:.
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fulltext access Le test haute résolution de circuits imprimés nus
Vaucher C.
Institut National Polytechnique de Grenoble - INPG (1993-11-25), Louis Balme (Dir.) [tel-00343737 - version 1]
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The standard mirror boards (SMBs) concept-An innovative improvement of traditional ATE for up to 10 mil bare board testing
Vaucher C. et al
In Proceedings.-International-Test-Conference-1993-Cat.-No.93CH3356-3 - Proceedings.-International-Test-Conference-1993-Cat.-No.93CH3356-3, United States (1993) [hal-00016096 - version 1]
Synthesis of large controllers using ROM or PLA generators
Gerbaux L. et al
IFIP-Transactions-A-Computer-Science-and-Technology A-22 (1993) 47-59 [hal-00015227 - version 1]
Generation of optimized datapaths: bit-slice versus standard cells
Leveugle R. et al
IFIP-Transactions-A-Computer-Science-and-Technology A-22 (1993) 153-66 [hal-00015225 - version 1]
Clocking scheme selection for circuits made up of a controller and a datapath
Safinia C. et al
IFIP-Transactions-A-Computer-Science-and-Technology A-22 (1993) 293-308 [hal-00015223 - version 1]
Logic synthesis for automatic layout
Abouzeid P. et al
IFIP-Transactions-A-Computer-Science-and-Technology A-22 (1993) 335-43 [hal-00015219 - version 1]
A synthesis tool for fault-tolerant finite state machines
Leveugle R. et al
In Digest-of-Papers-FTCS-23-The-Twenty-Third-International-Symposium-on-Fault-Tolerant-Computing - Digest-of-Papers-FTCS-23-The-Twenty-Third-International-Symposium-on-Fault-Tolerant-Computing, France (1993) [hal-00015128 - version 1]
Influence of error correlations on the signature analysis aliasing
Leveugle R. et al
In Proceedings-1993-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.93CH3335-7 - Proceedings-1993-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.93CH3335-7, United States (1993) [hal-00015123 - version 1]
Analysis and comparison of fault tolerant FSM architecture based on SEC codes
Rochet R. et al
In Proceedings.-The-IEEE-International-Workshop-on-Defect-and-Fault-Tolerance-in-VLSI-Systems-Cat.-No.93TH0571-0 - Proceedings.-The-IEEE-International-Workshop-on-Defect-and-Fault-Tolerance-in-VLSI-Systems-Cat.-No.93TH0571-0, Italy (1993) [hal-00015120 - version 1]
Optimized state assignment of single fault tolerant FSMs based on SEC codes
Leveugle R.
In 30th-Design-Automation-Conference.-Proceedings-1993-IEEE-Cat.-No.93CH3262-3 - 30th-Design-Automation-Conference.-Proceedings-1993-IEEE-Cat.-No.93CH3262-3, United States (1993) [hal-00015117 - version 1]
Design and comparison of GaAs and CMOS redundant divider
Moussa I. et al
In ESSCIRC-93.-Nineteenth-European-Solid-State-Circuits-Conference.-Proceedings. - ESSCIRC-93.-Nineteenth-European-Solid-State-Circuits-Conference.-Proceedings., Spain (1993) [hal-00014942 - version 1]
VLSI design of on-line add/multiply algorithms
Skaf A. et al
In Proceedings-1993-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.93CH3335-7. - Proceedings-1993-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.93CH3335-7., United States (1993) [hal-00014941 - version 1]
Design of a VLSI circuit for on-line evaluation of several elementary functions using their Taylor expansions
Bajard J.-C. et al
In Proceedings.-International-Conference-on-Application-Specific-Array-Processors-Cat.-No.93TH0572-8. 1993: - Proceedings.-International-Conference-on-Application-Specific-Array-Processors-Cat.-No.93TH0572-8. 1993:, Italy (1993) [hal-00014928 - version 1]
Quiescent current estimation based on quality requirements
Vargas F. Hernan et al
In Digest-of-Papers.-Eleventh-Annual-1993-IEEE-VLSI-Test-Symposium-Cat.-No.93TH0537-1 - Digest-of-Papers.-Eleventh-Annual-1993-IEEE-VLSI-Test-Symposium-Cat.-No.93TH0537-1, United States (1993) [hal-00013997 - version 1]
Finitely self-checking circuits and their application on current sensors
Nicolaidis M.
In Digest-of-Papers.-Eleventh-Annual-1993-IEEE-VLSI-Test-Symposium-Cat.-No.93TH0537-1 - Digest-of-Papers.-Eleventh-Annual-1993-IEEE-VLSI-Test-Symposium-Cat.-No.93TH0537-1, United States (1993) [hal-00013994 - version 1]
Trade-offs in scan path and BIST implementations for RAMs
Nicolaidis M. et al
In : Proceedings-of-ETC-93.-Third-European-Test-Conference-Cat.-No.93TH0494-5 - : Proceedings-of-ETC-93.-Third-European-Test-Conference-Cat.-No.93TH0494-5, Netherlands (1993) [hal-00013992 - version 1]
Checking signatures on boundary scan boards
Castro-Alves V. et al
In Proceedings-of-ETC-93.-Third-European-Test-Conference-Cat.-No.93TH0494-5 - Proceedings-of-ETC-93.-Third-European-Test-Conference-Cat.-No.93TH0494-5, Netherlands (1993) [hal-00013990 - version 1]
Exact aliasing computation and/or aliasing free design for RAM BIST
Yarmolik V.-N. et al
In Records-of-the-1993-IEEE-International-Workshop-on-Memory-Testing-Cat.-No.93TH0554-6 - Records-of-the-1993-IEEE-International-Workshop-on-Memory-Testing-Cat.-No.93TH0554-6, France (1993) [hal-00013985 - version 1]