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Communications avec actes

Custom Integrated Circuits Conference (CICC'11), San Jose, Ca. : États-Unis (2011)

Bottom-up digital system-level reliability modeling

N.R. Amador1, V. Huard1, E. Pion1, F. Cacho1, D. Croain1, V. Robert1, S. Engels1, P. Flatresse1, L. Anghel2

We demonstrate here for the first time that it is possible by a bottom-up approach to build transistor- and gate-level models with enough accuracy to allow direct comparison with experimental degradations at system-level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy.

1 :	ST-CROLLES - STMicroelectronics (Crolles)
2 :	TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture

Mots Clés : integrated circuit reliability – delay – logic gates

hal-00651936, version 1

http://hal.archives-ouvertes.fr/hal-00651936

oai:hal.archives-ouvertes.fr:hal-00651936

Contributeur : Lucie Torella <>

Soumis le : Mercredi 14 Décembre 2011, 15:31:31

Dernière modification le : Mercredi 14 Décembre 2011, 15:31:31