284 articles – 2152 Notices  [english version]
Fiche concise Articles dans des revues avec comité de lecture
Adaptive inter-layer message routing in 3D networks-on-chip
Rusu C. et al
Microprocessors and Microsystems 35, 7 (2011) 613-631 - http://hal.archives-ouvertes.fr/hal-00650162
C. Rusu1, L. Anghel2, D. Avresky3
1 :  EADS, Corporate Research Center
http://www.eads.com
EADS Paris
EADS France S.A.S. · 37, boulevard de Montmorency · 75781 Paris Cedex 16 ·
France
2 :  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
http://tima.imag.fr/
CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG)
46 Av Félix Viallet 38031 GRENOBLE CEDEX 1
France
3 :  IRIANC - International Research Institute for Autonomic Network Computing
http://www.irianc.com/
institut de recherche
Boston, MA, USA / Munich. Germany
États-Unis
Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique
Adaptive inter-layer message routing in 3D networks-on-chip
Existing routing algorithms for 3D deal with regular mesh/torus 3D topologies. Today 3D NoCs are quite irregular, especially those with heterogeneous layers. In this paper, we present a routing algorithm targeting 3D networks-on-chip (NoCs) with incomplete sets of vertical links between adjacent layers. The routing algorithm tolerates multiple link and node failures, in the case of absence of NoC partitioning. In addition, it deals with congestion. The routing algorithm for 3D NoCs preserves the deadlock-free propriety of the chosen 2D routing algorithms. It is also scalable and supports a local reconfiguration that complements the reconfiguration of the 2D routing algorithms in case of failures of nodes or links. The algorithm incurs a small overhead in terms of exchanged messages for reconfiguration and does not introduce significant additional complexity in the routers. Theoretical analysis of the 3D routing algorithm is provided and validated by simulations for different traffic loads and failure rates.
Anglais

10.1016/j.micpro.2011.06.008
Microprocessors and Microsystems
internationale
2011
35
7
613-631

networks on chip
PACS 85.42