| Auteur(s) |
S. Guilley1, S. Chaudhuri1, L. Sauvage1, J.-L. Danger1, T. Beyrouthy2, L. Fesquet2 |
| Laboratoire |
|
| Domaine |
Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique
|
| Titre |
Updates on the Potential of Clock-Less Logics to Strengthen Cryptographic Circuits against Side-Channel Attacks |
| Résumé |
Cryptographic circuits are subject to sneak attacks that target directly their implementation. So-called side-channel attacks consists in observing dynamic circuit emanations in order to derive information about the secrets itconceals. Clock-less logic styles natively make side-channel attacks difficult, because of the absence of timing references for the algorithm beginning or ending. We present two ways to implement secure clockless cryptographic circuits. The first one is based on a local synchronization at the gate level, and helps achieving close to constant emanations. The second one is more audacious as it is based merely on removing all synchronization. This approach proves to be very promising in terms of protection against sidechannel attacks, while keeping a reasonable overhead both in terms of cost and performances. |
| Langue du texte intégral |
Anglais |
|
| DOI |
10.1109/ICECS.2009.5411008 |
| Titre de l'ouvrage |
IEEE International Conference on Electronics and Systems (ICECS'09) |
| Audience |
internationale |
| Date de publication |
2009 |
| Page, identifiant, ... |
351 - 354 |
| Éditeur commercial |
IEEE Computer Society |
| Série/Collection |
Proceedings |
|
| Titre de la conférence |
IEEE International Conference on Electronics and Systems (ICECS'09) |
| Date de la conférence |
13/12/2009 |
| Date de la conférence (fin) |
16/12/2009 |
| Ville |
Hammamet |
| Pays |
Tunisie |
|
| Mots Clés |
cryptographic chips – side channel attacks |
| Classification |
PACS 85.42 |
| Commentaire |
ISBN 978-1-4244-5090-9 |
|
