282 articles – 2123 Notices  [english version]
Fiche concise Articles dans des revues avec comité de lecture
Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation
Leveugle R. et al
Electron-Technology 32(3) (1999) 282-7 - http://hal.archives-ouvertes.fr/hal-00015077
R. Leveugle1, 2, R. Ubar1
1 :  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
http://tima.imag.fr/
CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG)
46 Av Félix Viallet 38031 GRENOBLE CEDEX 1
France
2 :  CSI - CSI, Inst. Nat. Polytech. de Grenoble, France
http://inpg.fr
Institut National Polytechnique de Grenoble (INPG)
Grenoble
France
Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique
Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation
A method is presented for creating decision diagrams (DD) from multi-process VHDL descriptions for test generation purposes. Each process in the VHDL description will be represented either by one or several DDs. To increase the efficiency of test generation, a method is given for compressing the model and collapsing faults by superposition of DDs. The method supports well functional test generation as well as hierarchical test synthesis if the low level implementation details can be provided. Experimental results are included to show the efficiency of using DDs in test generation.
Anglais

Electron-Technology
1999
32(3)
282-7

decision-diagrams-synthesis – clock-driven-multi-process-VHDL-descriptions – functional-test-generation – model-compression – collapsing-faults – DD-superposition – hierarchical-test-synthesis – low-level-implementation-details – ATPG-
PACS 85.42