285 articles – 2153 Notices  [english version]
Fiche détaillée Communications avec actes
Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6., Paris : France (1994)
A VLSI implementation of parallel fast Fourier transform
A. VACHER1, M. Benkhebbab1, A. Guyot1, T. Rousseau1, A. Skaf1

This paper presents the design of a VLSI circuit to perform the Fourier transform using on-line most-significant-digit-first arithmetic. First, the principles of the pipelined fast Fourier transform are recalled, and a folded pipeline is introduced. Then on-line operators and operator merging rules are used to design a cost effective butterfly operator. Finally a circuit with 8 butterflies is described and compared to other realizations.
1 :  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
VLSI-implementation – parallel-fast-Fourier-transform – VLSI-circuit-design – on-line-most-significant-digit-first-arithmetic – pipelined-fast-Fourier-transform – folded-pipeline – on-line-operators – operator-merging-rules – cost-effective-butterfly-operator