| Auteur(s) |
R.P. Ribas1, A. Guyot2 |
| Laboratoire |
|
| Domaine |
Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique
|
| Titre |
DCFL- and DPTL-based approaches to self-timed GaAs circuits |
| Résumé |
This paper presents two GaAs MESFET-based methodologies to design self-timed circuits. The first approach uses direct-coupled FET logic (DCFL) to implement Boolean equations in sum-of-sums form, resulting in a simple and fast way to design hazard-free functional blocks in asynchronous systems. The second approach deals with an adaptation of the ratioless differential pass-transistor logic (DPTL) technique to construct such functional blocks. This approach is demonstrated to be very effective in minimizing area overhead and power consumption. The methodologies are described and validated through a radix-2 redundant divider implementation. |
| Langue du texte intégral |
Anglais |
|
| Titre de l'ouvrage |
ESSCIRC-'95.-Twenty-First-European-Solid-State-Circuits-Conference.-Proceedings. |
| Date de publication |
1995 |
| Page, identifiant, ... |
186-9 |
| Éditeur commercial |
Editions Frontieres, Gif sur Yvette, France |
|
| Titre de la conférence |
ESSCIRC-'95.-Twenty-First-European-Solid-State-Circuits-Conference.-Proceedings. |
| Date de la conférence |
1995 |
| Ville |
Lille |
| Pays |
France |
|
| Mots Clés |
self-timed-GaAs-circuits – GaAs-MESFET – direct-coupled-FET-logic – Boolean-equations – asynchronous-systems – ratioless-differential-pass-transistor-logic – power-consumption – radix-2-redundant-divider-implementation – VLSI- – GaAs- |
| Classification |
PACS 85.42 |
| Commentaire |
ISBN: 2863321803 |
|
