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DCFL- and DPTL-based approaches to self-timed GaAs circuits
Ribas R.P. et al
Dans ESSCIRC-'95.-Twenty-First-European-Solid-State-Circuits-Conference.-Proceedings. - ESSCIRC-'95.-Twenty-First-European-Solid-State-Circuits-Conference.-Proceedings., Lille : France (1995) - http://hal.archives-ouvertes.fr/hal-00014927
R.P. Ribas1, A. Guyot2
1 :  Univ. Federal do Rio Grande do Sul
Univ. Federal do Rio Grande do Sul
UFRGS, CxP 15064, CEP915O1-970, Porto Alegre
France
2 :  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
http://tima.imag.fr/
CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG)
46 Av Félix Viallet 38031 GRENOBLE CEDEX 1
France
Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique
DCFL- and DPTL-based approaches to self-timed GaAs circuits
This paper presents two GaAs MESFET-based methodologies to design self-timed circuits. The first approach uses direct-coupled FET logic (DCFL) to implement Boolean equations in sum-of-sums form, resulting in a simple and fast way to design hazard-free functional blocks in asynchronous systems. The second approach deals with an adaptation of the ratioless differential pass-transistor logic (DPTL) technique to construct such functional blocks. This approach is demonstrated to be very effective in minimizing area overhead and power consumption. The methodologies are described and validated through a radix-2 redundant divider implementation.
Anglais

ESSCIRC-'95.-Twenty-First-European-Solid-State-Circuits-Conference.-Proceedings.
1995
186-9
Editions Frontieres, Gif sur Yvette, France

ESSCIRC-'95.-Twenty-First-European-Solid-State-Circuits-Conference.-Proceedings.
1995
Lille
France

self-timed-GaAs-circuits – GaAs-MESFET – direct-coupled-FET-logic – Boolean-equations – asynchronous-systems – ratioless-differential-pass-transistor-logic – power-consumption – radix-2-redundant-divider-implementation – VLSI- – GaAs-
PACS 85.42
ISBN: 2863321803