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Proceedings-EURO-DAC-'96.-European-Design-Automation-Conference-with-EURO-VHDL-'96-and-Exhibition-Cat.-No.96CB36000, Geneva : Suisse (1996)

Automatic diagnosis may replace simulation for correcting simple design errors

A. Wahba1, D. Borrione2

An automated tool for diagnosing simple design errors in VHDL description is presented. The tool is tested on benchmark circuits, and the results show that the error is localized precisely, after the application of a small number of specially generated test patterns. This tool is now integrated within the PREVAIL/sup TM/ system, and is being tested on industrial circuits.

1 :	MENTOR GRAPHICS EGYPT - Mentor Graphics Egypt
2 :	TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture

Mots Clés : automatic-diagnosis – simple-design-error-correction – VHDL-description – benchmark-circuits – specially-generated-test-patterns – industrial-circuits – combinational-circuits – sequential-circuits – test-pattern-generation

hal-00014217, version 1

http://hal.archives-ouvertes.fr/hal-00014217

oai:hal.archives-ouvertes.fr:hal-00014217

Contributeur : Lucie Torella <>

Soumis le : Mardi 22 Novembre 2005, 10:06:54

Dernière modification le : Jeudi 13 Avril 2006, 13:50:27