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Design of self-testing RAMs Yarmolik V.-N. et al Russian Microelectronics May-June ; 24(3) (1995) 186-90 - http://hal.archives-ouvertes.fr/hal-00013902

Auteur(s)	V.-N. Yarmolik1, G.-R. Memetov1, M. Nicolaidis ()1, 2
Laboratoire	1 :  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture http://tima.imag.fr/ CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG) 46 Av Félix Viallet 38031 GRENOBLE CEDEX 1 France 2 :  IROC TECHNOLOGIES - iROc Technologies http://www.iroctech.com/ Cadence Connection – EDA Consortium – FSA – Cubic Micro WTC Po Box 1510 Grenoble France
Domaine	Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique
Titre	Design of self-testing RAMs
Résumé	RAMs built in complex VLSIs are frequently used at present. Self-testing is the most appropriate testing method for these devices. RAM testing should be as complete as possible because RAM is one of the major parts in any computer system. In this work we propose a self-testing RAM design that allows detection of all faults of given types. As a result, a self-testing RAM with 100-% detectability of certain faults was designed.
Langue du texte intégral	Anglais
Journal	Russian Microelectronics
Date de publication	1995
Volume	May-June ; 24(3)
Page, identifiant, ...	186-90
Mots Clés	self-testing-RAMs – complex-VLSI – testing-method – fault-detection – detectability- – memory-testing – linear-compression – testing-algorithms
Classification	PACS 85.42

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