| Auteur(s) |
D. Alexandrescu1, L. Anghel ( )1, M. Nicolaidis ()1, 2 |
| Laboratoire |
|
| Domaine |
Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique
|
| Titre |
New methods for evaluating the impact of single event transients in VDSM ICs |
| Résumé |
This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell. Fault injection procedures and a fast fault simulation algorithm for transient faults were implemented around an event driven simulator. A statistical analysis was implemented to organize data sampled from simulations. The benchmarks show that the proposed algorithm is capable of injecting and simulating a large number of transient faults in complex designs. Also specific optimizations have been carried out, thus greatly reducing the simulation time compared to a sequential fault simulation approach. |
| Langue du texte intégral |
Anglais |
|
| DOI |
10.1109/DFTVS.2002.1173506 |
| Titre de l'ouvrage |
Proceedings-17th-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems.-DFT-2002 |
| Date de publication |
2002 |
| Page, identifiant, ... |
99-107 |
| Éditeur commercial |
IEEE Comput. Soc, Los Alamitos, CA, USA |
|
| Titre de la conférence |
Proceedings-17th-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems.-DFT-2002 |
| Date de la conférence |
2002 |
| Ville |
Vancouver, BC |
| Pays |
Canada |
|
| Mots Clés |
single-event-transient – VDSM-ICs – very-deep-submicron-ICs – SET-fault-simulation-technique – probability- – combinational-logic – storage-cell |
| Classification |
PACS 85.42 |
| Commentaire |
ISBN: 0769518311 |
|
