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New methods for evaluating the impact of single event transients in VDSM ICs
Alexandrescu D. et al
Dans Proceedings-17th-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems.-DFT-2002 - Proceedings-17th-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems.-DFT-2002, Vancouver, BC : Canada (2002) - http://hal.archives-ouvertes.fr/hal-00013736
D. Alexandrescu1, L. Anghel ()1, M. Nicolaidis ()1, 2
1 :  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
http://tima.imag.fr/
CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG)
46 Av Félix Viallet 38031 GRENOBLE CEDEX 1
France
2 :  IROC TECHNOLOGIES - iROc Technologies
http://www.iroctech.com/
Cadence Connection – EDA Consortium – FSA – Cubic Micro
WTC Po Box 1510 Grenoble
France
Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique
New methods for evaluating the impact of single event transients in VDSM ICs
This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell. Fault injection procedures and a fast fault simulation algorithm for transient faults were implemented around an event driven simulator. A statistical analysis was implemented to organize data sampled from simulations. The benchmarks show that the proposed algorithm is capable of injecting and simulating a large number of transient faults in complex designs. Also specific optimizations have been carried out, thus greatly reducing the simulation time compared to a sequential fault simulation approach.
Anglais

10.1109/DFTVS.2002.1173506
Proceedings-17th-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems.-DFT-2002
2002
99-107
IEEE Comput. Soc, Los Alamitos, CA, USA

Proceedings-17th-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems.-DFT-2002
2002
Vancouver, BC
Canada

single-event-transient – VDSM-ICs – very-deep-submicron-ICs – SET-fault-simulation-technique – probability- – combinational-logic – storage-cell
PACS 85.42
ISBN: 0769518311