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DLS: A scheduling algorithm for high-level synthesis in VH
O'Brien K. et al
in (1993)-Proceedings-The-European-Conference-on-Design-Automation-with-the-European-Event-in-ASIC-Design - (1993) - http://hal.archives-ouvertes.fr/hal-00008030
K. O'Brien1, M. Rahmouni1, A.A. Jerraya ()1
1 :  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
http://tima.imag.fr/
CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG)
46 Av Félix Viallet 38031 GRENOBLE CEDEX 1
France
Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique
DLS: A scheduling algorithm for high-level synthesis in VH
Dynamic loop scheduling, an algorithm that can efficiently schedule large, control-flow dominated designs, written in VHDL is presented. It compares favorably with results produced by other control-flow oriented approaches such as path-based scheduling, but avoids the path explosion problem. In addition, the VHDL accepted by the scheduler is quite comprehensive, including nested branches, loops (whose conditions can be compounded), loop exit statements and procedure calls. The algorithm forms an integral part of the AMICAL data-path compiler.
Anglais

[1993]-Proceedings-The-European-Conference-on-Design-Automation-with-the-European-Event-in-ASIC-Design
1993
393-7
IEEE Computer Society Press, Los Alamitos, CA, USA

1993

dynamic-loop-scheduling – scheduling-algorithm – high-level-synthesis – VHDL- – control-flow-dominated-designs – nested-branches – loop-exit-statements – procedure-calls – AMICAL-data-path-compiler
PACS 85.42