| Auteur(s) |
K. O'Brien1, M. Rahmouni1, A.A. Jerraya ( )1 |
| Laboratoire |
|
| Domaine |
Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique
|
| Titre |
DLS: A scheduling algorithm for high-level synthesis in VH |
| Résumé |
Dynamic loop scheduling, an algorithm that can efficiently schedule large, control-flow dominated designs, written in VHDL is presented. It compares favorably with results produced by other control-flow oriented approaches such as path-based scheduling, but avoids the path explosion problem. In addition, the VHDL accepted by the scheduler is quite comprehensive, including nested branches, loops (whose conditions can be compounded), loop exit statements and procedure calls. The algorithm forms an integral part of the AMICAL data-path compiler. |
| Langue du texte intégral |
Anglais |
|
| Titre de l'ouvrage |
[1993]-Proceedings-The-European-Conference-on-Design-Automation-with-the-European-Event-in-ASIC-Design |
| Date de publication |
1993 |
| Page, identifiant, ... |
393-7 |
| Éditeur commercial |
IEEE Computer Society Press, Los Alamitos, CA, USA |
|
| Date de la conférence |
1993 |
|
| Mots Clés |
dynamic-loop-scheduling – scheduling-algorithm – high-level-synthesis – VHDL- – control-flow-dominated-designs – nested-branches – loop-exit-statements – procedure-calls – AMICAL-data-path-compiler |
| Classification |
PACS 85.42 |
|
