248 articles – 2008 Notices  [english version]
.:. Consultation > Liste par auteurs > Anghel .:.
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A predictive bottom-up hierarchical approach to digital system reliability
Huard V. et al
In Proc. of IEEE International Reliability Physics Symposium (IRPS'12) - IEEE International Reliability Physics Symposium (IRPS'12), United States (2012) [hal-00747363 - version 1]
Electromigration degradation mechanism analysis of SnAgCu interconnects for eWLB package
Frank T. et al
In Proc. of IEEE International Reliability Physics Symposium (IRPS'12) - IEEE International Reliability Physics Symposium (IRPS'12), United States (2012) [hal-00747359 - version 1]
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis
Pasca V. et al
Journal of Electronic Testing: Theory and Application 28 (2012) Online First™, 3 August [hal-00744561 - version 1]
Design for Test and Reliability in Ultimate CMOS
Nicolaidis M. et al
In Proc. of Design, Automation and Test in Europe (DATE'12) - Design, Automation and Test in Europe (DATE'12), Germany (2012) [hal-00688282 - version 1]
On the Dependability of 3D Interconnects
Anghel L.
In Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'12) - Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'12), France (2012) [hal-00677047 - version 1]
Towards Low-cost Soft Error Mitigation in SRAM-based FPGAs: a Case Study on AT40K
Ferron J. et al
In Proc. of 3rd IEEE Latin American Symposium on Circuits and Systems (LASCAS'12) - 3rd IEEE Latin American Symposium on Circuits and Systems (LASCAS'12), Mexico (2012) [hal-00676825 - version 1]
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
Pasca V. et al
Journal of Electronic Testing 28, 1 (2012) 137-150 [hal-00650169 - version 1]
Criticality of Configuration Bits in SRAM-based FPGAs: Predictive Analysis and Experimental Results
Anghel L. et al
In Proc. of Workshop on Design for Reliability and Variability (DRVW'11) - Workshop on Design for Reliability and Variability (DRVW'11), United States (2011) [hal-00624239 - version 1]
Bottom-up digital system-level reliability modeling
Amador N.R. et al
In Custom Integrated Circuits Conference (CICC'11), San Jose, Ca., USA, 19-21 September - Custom Integrated Circuits Conference (CICC'11), United States (2011) [hal-00651936 - version 1]
Electromigration Behavior of 3D-IC TSV
Frank T. et al
In Proc. of Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D IC), in conjuction with ITC - Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D IC), in conjuction with ITC, United States (2011) [hal-00651930 - version 1]
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor
Yu H. et al
In Proc. of 16th IEEE European Test Symposium (ETS'11) - 16th IEEE European Test Symposium (ETS'11), Norway (2011) [hal-00651920 - version 1]
I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems
Nicolaidis M. et al
In Proc. of 16th IEEE European Test Symposium (ETS'11) - 16th IEEE European Test Symposium (ETS'11), Norway (2011) [hal-00651916 - version 1]
Memory BIST with address programmability
Fradi A. et al
In Proc. of IEEE international On Line Testing Symposium (IOLT'11) - IEEE international On Line Testing Symposium (IOLT'11), Greece (2011) [hal-00651913 - version 1]
Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis
Pasca V. et al
In Proc. of IEEE Latin America Test Symposium Workshop (LATW'11) - IEEE Latin America Test Symposium Workshop (LATW'11), Brazil (2011) [hal-00651437 - version 1]
Designing cost-effective robust systems by accurate reliability modeling
Anghel L. et al
In Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'11) - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'11), Canada (2011) [hal-00651413 - version 1]
On the Dependability of 3D Interconnects
Anghel L. et al
In Proc. of Dependability Issues in Deep-submicron Technologies Workshop (DDT'11) - Dependability Issues in Deep-submicron Technologies Workshop (DDT'11), Norway (2011) [hal-00650195 - version 1]
Adaptive inter-layer message routing in 3D networks-on-chip
C. R. et al
Microprocessors and Microsystems 35, 7 (2011) 613-631 [hal-00650162 - version 1]
Analysis of configuration bit criticality in designs implemented with SRAM-based FPGAs
Ferron J. et al
Dans Proc. of IEEE Symposium on Industrial Electronics & Applications (ISIEA'11) - IEEE Symposium on Industrial Electronics & Applications (ISIEA'11), Malaisie (2011) [hal-00643903 - version 1]
Resistance Increase Due to Electromigration Induced Depletion Under TSV
Frank T. et al
In Proc of IEEE International Reliability Physics Symposium (IRPS'11) - IEEE International Reliability Physics Symposium (IRPS'11), Monterey, CA, USA, April 10-14, United States (2011) [hal-00599391 - version 1]
Reliability approach of high density Through Silicon Via (TSV)
Frank T. et al
In Proc. of 12th Electronics Packaging Technology Conference (EPTC'10) - 12th Electronics Packaging Technology Conference (EPTC'10), Singapore (2010) [hal-00599560 - version 1]