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Cells: A Framework for Designing Robust Tera-Device Processors Nicolaidis M. Dans Proc of Workshop on Low Power Design Impact on Test and Reliability (LPonTR) - Workshop on Low Power Design Impact on Test and Reliability (LPonTR), France (2012) [hal-00815963 - version 1]

Controling variability and energy by design Fesquet L. In CMOS Emerging Technologies - CMOS Emerging Technologies, Canada (2012) [hal-00747376 - version 1]

On the Dependability of 3D Interconnects Anghel L. In Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'12) - Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'12), France (2012) [hal-00677047 - version 1]

SoC for biomedical applications: trends and challenges Mir S. In Proc. of 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'11) - 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'11), Hong Kong (2011) [hal-00688248 - version 1]

Criticality of Configuration Bits in SRAM-based FPGAs: Predictive Analysis and Experimental Results Anghel L. et al In Proc. of Workshop on Design for Reliability and Variability (DRVW'11) - Workshop on Design for Reliability and Variability (DRVW'11), United States (2011) [hal-00624239 - version 1]

Designing Single-Chip Massively Parallel Tera-Device Processors: Towards the Terminator Chip Nicolaidis M. In Proc. of 29th IEEE VLSI TEST SYMPOSIUM (VTS'11) - 29th IEEE VLSI TEST SYMPOSIUM (VTS'11), United States (2011) [hal-00624246 - version 1]

Localization of Damaged Resources in NoC Based Shared-Memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure Zhang Z. et al The 29th IEEE VLSI Test Symposium (VTS), United States (2011) [hal-00591807 - version 1]

An analytical model for Many-Functionally Asymmetric Core SoC Architectures Pétrot F. In 11th International Forum on Embedded MPSoC and Multicore - 11th International Forum on Embedded MPSoC and Multicore, France (2011) [hal-00680327 - version 1]

Utilisation de techniques de traduction binaire dynamique pour la simulation rapide et précise des MPSoCs Pétrot F. In Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (Fetch'11) - Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (Fetch'11), Canada (2011) [hal-00680323 - version 1]

Effects of Radiation on Integrated Circuits : origines, mitigation techniques, test and real-life experiments Velazco R. In Proc. of Conférence magistrale in Congreso de Informática Univ. Tecnológica de Machala (III CIU/) - Conférence magistrale in Congreso de Informática Univ. Tecnológica de Machala (III CIU/), Ecuador (2011) [hal-00674535 - version 1]

Soft-error-rate prediction for programmable circuits: methodology, tools and studied cases Velazco R. In Proc of Conférence magistrale in Congreso Internacional de Ingenieria Eléctrica, Electrónica, Sistemas y Ramas Afines (XVIII INTERCON) - Conférence magistrale in Congreso Internacional de Ingenieria Eléctrica, Electrónica, Sistemas y Ramas Afines (XVIII INTERCON), Peru (2011) [hal-00674531 - version 1]

Thinking and Designing Differently: The Asynchronous Alternative Fesquet L. In Proc. of Dresden Microelectronic Academy - Dresden Microelectronic Academy, Germany (2011) [hal-00671323 - version 1]

Designing cost-effective robust systems by accurate reliability modeling Anghel L. et al In Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'11) - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'11), Canada (2011) [hal-00651413 - version 1]

On the Dependability of 3D Interconnects Anghel L. et al In Proc. of Dependability Issues in Deep-submicron Technologies Workshop (DDT'11) - Dependability Issues in Deep-submicron Technologies Workshop (DDT'11), Norway (2011) [hal-00650195 - version 1]

Adaptive Alternate Analog Test Stratigopoulos H. et al In Proc. of IEEE Latin-American Test Workshop (LATW'11) - IEEE Latin-American Test Workshop (LATW'11), Brazil (2011) [hal-00625043 - version 1]

Statistical Learning for Analog Circuit Testing Stratigopoulos H. In Proc. of International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'11) - Conference on International Design & Technology of Integrated Systems in Nanoscale Era (DTIS'11), Greece (2011) [hal-00625040 - version 1]

Implicit Test of High-Speed Analog Circuits Using Non-Intrusive Sensors Abdallah L. et al IEEE European Conference on Circuit Theory and Design (ECCTD'11), Sweden (2011) [hal-00625038 - version 1]

Fully Distributed Initialization Procedure for a 2D-Mesh NoC, Including Off Line BIST and Partial Deactivation of Faulty Components Zhang Z. et al The 16th IEEE International On-Line Testing Symposium (IOLTS), Greece (2010) [hal-00591795 - version 1]

Single Events on Digital Integrated Circuits Velazco R. In BETCON: Bolivian Engineering and Technology Congress - BETCON: Bolivian Engineering and Technology Congress, Bolivia, Plurinational State Of (2010) [hal-00560592 - version 1]

Density Estimation for Analog/RF Test Problem Solving Mir S. et al VLSI Test Symposium (VTS), United States (2010) [hal-00490709 - version 1]