282 articles – 2123 references  [version française]
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fulltext access Le test unifié de cartes appliqué à la conception de systèmes fiables
Lubaszewski M.
Institut National Polytechnique de Grenoble - INPG (20/06/1994), COURTOIS B. (Dir.) [tel-00010759 - version 1]
fulltext access Etude des liens entre la synthèse architecturale et la synthèse au niveau transfert de registres
Aichouchi M.
Institut National Polytechnique de Grenoble - INPG (1994-06-20), JERRAYA A. A. (Dir.) [tel-00010758 - version 1]
Netlist automatic extractor: "An image processing based software for bare board test data generation"
Benali A. et al
In Proceedings-of-the-Third-Asian-Test-Symposium-Cat.-No.94TH8016 - Proceedings-of-the-Third-Asian-Test-Symposium-Cat.-No.94TH8016, Japan (1994) [hal-00016097 - version 1]
Test of single fault tolerant controllers in VLSI circuits
Leveugle R.
IFIP-Transactions-A-Computer-Science-and-Technology A-42 (1994) 123-32 [hal-00015217 - version 1]
Taking advantage of ASICs to improve dependability with very low overheads (PLC)
Michel T. et al
In Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6 - Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6, France (1994) [hal-00015209 - version 1]
Taking advantage of high level functional information to refine timing analysis and timing information
Safinia C. et al
In Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6 - Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6, France (1994) [hal-00015207 - version 1]
The Hyeti defect tolerant microprocessor: a practical experiment and its cost-effectiveness analysis
Leveugle R. et al
IEEE Transactions on Computers Dec. ; 43(12) (1994) 1398-406 [hal-00015204 - version 1]
Alternative approaches to fault detection in FSMs
Leveugle R. et al
In 1994-Proceedings.-The-IEEE-International-Workshop-on-Defect-and-Fault-Tolerance-in-VLSI-Systems-Cat.-No.94TH78009 - 1994-Proceedings.-The-IEEE-International-Workshop-on-Defect-and-Fault-Tolerance-in-VLSI-Systems-Cat.-No.94TH78009, Canada (1994) [hal-00015112 - version 1]
Design of a GaAs redundant divider
Moussa I. et al
IFIP-Transactions-A-Computer-Science-and-Technology A-42: (1994) 63-72 [hal-00014956 - version 1]
A VLSI circuit for on-line polynomial computing: application to exponential, trigonometric and hyperbolic functions
Skaf A. et al
IFIP-Transactions-A-Computer-Science-and-Technology A-42 (1994) 93-100 [hal-00014954 - version 1]
Error-speed compromise for FFT VLSI
VACHER A. et al
Dans Proceedings-of-the-26th-Southeastern-Symposium-on-System-Theory-Cat.-No.94TH0599-1 - Proceedings-of-the-26th-Southeastern-Symposium-on-System-Theory-Cat.-No.94TH0599-1, États-Unis (1994) [hal-00014952 - version 1]
A VLSI implementation of parallel fast Fourier transform
VACHER A. et al
Dans Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6. - Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6., France (1994) [hal-00014947 - version 1]
Combinational digit-set converters for hybrid radix-4 arithmetic
Montalvo L.-A. et al
In Proceedings-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.94CH35712. - Proceedings-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.94CH35712., United States (1994) [hal-00014946 - version 1]
CMOS implementation of a hybrid radix-4 divider
Montalvo L.-A. et al
In ESSCIRC-'94.-Twentieth-European-Solid-State-Circuits-Conference.-Proceedings. - ESSCIRC-'94.-Twentieth-European-Solid-State-Circuits-Conference.-Proceedings., Germany (1994) [hal-00014940 - version 1]
On-line hardware implementation for complex exponential and logarithm
Skaf A. et al
In ESSCIRC-'94.-Twentieth-European-Solid-State-Circuits-Conference.-Proceedings. - ESSCIRC-'94.-Twentieth-European-Solid-State-Circuits-Conference.-Proceedings., Germany (1994) [hal-00014939 - version 1]
A process algebra interpretation of a verification oriented overlanguage of VHDL
Bayol C. et al
In Proceedings-EURO-DAC-'94-with-EURO-VHDL-'94-IEEE-Cat.-No.94CH35704. - Proceedings-EURO-DAC-'94-with-EURO-VHDL-'94-IEEE-Cat.-No.94CH35704., France (1994) [hal-00014238 - version 1]
Fault secure property versus strongly code disjoint checkers
Nicolaidis M.
IEEE-Transactions-on-Computer-Aided-Design-of-Integrated-Circuits-and-Systems May ; 13(5) (1994) 651-8 [hal-00013945 - version 1]
Efficient implementations of self-checking multiply and divide arrays
Nicolaidis M. et al
In Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6. - Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6., France (1994) [hal-00013943 - version 1]
Efficient UBIST for RAMs
Nicolaidis M.
In Proceedings-12th-IEEE-VLSI-Test-Symposium-Cat.-No.94TH0645-2. 1994: - Proceedings-12th-IEEE-VLSI-Test-Symposium-Cat.-No.94TH0645-2. 1994:, United States (1994) [hal-00013941 - version 1]