282 articles – 2128 references  [version française]
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Design, Automation and Test in Europe (DATE'12), Dresden : Germany (2012)
Enhancing Non-Linear Kernels by an Optimized Memory Hierarchy in a High Level Synthesis Flow
S. Mancini1, F. Rousseau1

Modern High Level Synthesis (HLS) tools are now efficient at generating RTL models from algo- rithmic descriptions of the target hardware accelerators but they still do not manage memory hierarchies.Mem- ory hierarchies are efficiently optimized by performing code transformations prior to HLS in frameworks which exploit the linearity of the mapping functions between loop indexes and memory references (called linear ker- nels). Unfortunately, non-linear kernels are algorithms which do not bene t of such classical frameworks, because of the disparity of the non-linear functions to compute their memory references. In this paper we propose a method to design non- linear kernels in a HLS ow, which can be seen as a code pre-processing. The method starts from an algorithmic description and generates an enhanced algorithmic de- scription containing both the non-linear kernel and an optimized memory hierarchy. The transformation and the associated optimization process provides a signi - cant gain when compared to a standard optimization. Experiments on benchmarks show an average reduction of 28% of the external memory traffic and about 32 times of the embedded memory size.
1:  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
hierarchical-high-level-synthesis