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Article in peer-reviewed journal

Journal of Electronic Testing: Theory and Application 27, 5, October (2011) pp

Reliability Limits of TMR Implemented in a SRAM-based FPGA: Heavy Ion Measures vs. Fault Injection Predictions

G. Foucard1, P. Peronnard2, R. Velazco1

This paper presents experimental results putting in evidence the potential weaknesses of a state-of-the-art fault tolerance strategy, the Triple Modular Redundancy (TMR), when implemented in SRAM-based FPGAs. HW/SW fault injection campaigns and accelerated radiation ground tests were performed to quantify the number of faults, Single Event Upsets (SEUs) required to obtain such critical failures.

1:	TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
2:	CERN - European Organization for Nuclear Research

Keyword(s) : SRAM-based FPGA – FAULT INJECTION

hal-00672434, version 1

http://hal.archives-ouvertes.fr/hal-00672434

oai:hal.archives-ouvertes.fr:hal-00672434

From: Lucie Torella <>

Submitted on: Tuesday, 21 February 2012 11:23:46

Updated on: Tuesday, 21 February 2012 11:23:46