279 articles – 2094 references  [version française]
Detailed view Article in peer-reviewed journal
Transactions on Design Automation of Electronic Systems 16, 3 (2011) article 35
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications
F. Abouzeid1, 2, S. Clerc1, F. Firmin1, M. Renaudin3, G. Sicard2

Ultra-low voltage is now a well-known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. At 0.33V, it performs at 600 kHz with a dynamic energy consumption reduced by a factor 14x from nominal 1.1V. Based on this design, experiments, and preliminary silicon results, two additional libraries were developed in order to enhance future ultra-low voltage circuit performance.
1:  ST MICROELECTRONICS - ST Microelectronics
2:  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
3:  TIEMPO SAS
CMOS – Low-power