251 articles – 2007 references  [version française]
Short view Conference proceedings
A Practical Approach to Single Event Transients Analysis for Highly Complex Designs
Alexandrescu D. et al
in Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems (DFT'11) - IEEE International Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems (DFT'11), Vancouver : Canada (2011) - http://hal.archives-ouvertes.fr/hal-00671330
D. Alexandrescu1, 2, E. Costenaro2, M. Nicolaidis ()1
1:  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
http://tima.imag.fr/
CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG)
46 Av Félix Viallet 38031 GRENOBLE CEDEX 1
France
2:  IROC TECHNOLOGIES - iROc Technologies
http://www.iroctech.com/
Cadence Connection – EDA Consortium – FSA – Cubic Micro
WTC Po Box 1510 Grenoble
France
Engineering Sciences/Micro and nanotechnologies/Microelectronics
A Practical Approach to Single Event Transients Analysis for Highly Complex Designs
Single Event Transients are considerably more difficult to model, simulate and analyze than the closely-related Single Event Upsets. The work environment may cause a myriad of distinctive transient pulses in various cell types that are used in widely different configurations. We present practical methods to help characterizing the standard cell library using dedicated tools and results from radiation testing. Furthermore, we analyze the SET propagation in logic networks using a standard (reference) serial fault simulation approach and an accelerated fault simulation technique, taking in account both logic and temporal considerations. The accelerated method provides similar results as the reference approach while offering a considerable increase in the simulation speed. However, the simulation approach may not be feasible for large (multi-million cells) designs that could benefit from static analysis methods. We benchmark the results of a static, probabilistic approach against the reference and accelerated methods. Finally, we discuss the integration of the SET analysis in a complete Soft Error Rate analysis flow.
English

10.1109/DFT.2011.18
Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems (DFT'11)
international
2011
155 - 163
IEEE Computer Society

IEEE International Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems (DFT'11)
2011-10-03
2011-10-05
Vancouver
Canada

Integrated Circuits – transient analysis – transistor – circuits..........
PACS 85.42
ISBN 978-1-4577-1713-0