282 articles – 2123 references  [version française]
Detailed view Conference proceedings
Workshop on Design for Reliability and Variability (DRVW'11), Dana Point, CA : United States (2011)
Variability-aware Task mapping strategies for Many-cores processor chips
F. Chaix1, G. Bizot1, M. Nicolaidis1, N. Zergainoh1

The advent of the Deep Submicron technology opens the way to many-cores processor chips. However, the variability and reliability of these processes poses new challenges. In particular, the mapping of applications will require specific strategies to leverage the plenty and diversity of the computation cores. In this regard, generic task mapping strategies are proposed to improve the energy efficiency of the applications, and compared for a synthetic application. In this contribution, we consider Streaming applications (e.g. video, audio or radio), which are modelled as fork-join Directed Acyclic Graph (DAG) of tasks. The Nearest node mapping strategy is used as a baseline, and minimizes the communication overhead. Then, a novel energy criterion is introduced to balance the computation and communication energy consumption. While increasing the communication energy, this strategy reduces the overall consumption by up to 20%. Finally, a mapping strategy based on variability regions improves slightly the energy efficiency of the application in the presence of systematic variations.
1:  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
processors