248 articles – 2008 references  [version française]
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Functional test compaction by statistical modelling of analogue circuits
Akkouche N. et al
Dans Proceedings of 13th IEEE International Mixed-Signals Testing Workhop (IMSTW'07) - 13th IEEE International Mixed-Signals Testing Workhop (IMSTW'07), Porto : Portugal (2007) - http://hal.archives-ouvertes.fr/hal-00173951
N. Akkouche1, A. Bounceur1, S. Mir1, E. Simeu1
1:  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
http://tima.imag.fr/
CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG)
46 Av Félix Viallet 38031 GRENOBLE CEDEX 1
France
Engineering Sciences/Micro and nanotechnologies/Microelectronics
Functional test compaction by statistical modelling of analogue circuits
In this paper, we address the problem of functional test compaction of analogue circuits by using a statistical model of the performances of the Circuit Under Test (CUT). The statistical model is obtained using data from a Monte-Carlo simulation and uses a multi-normal law to estimate the joint Probability Density Function (PDF) of the circuit performances at the design stage. The functional test compaction method is based on the minimization of the defect level, again at the design stage, that is calculated from the estimated PDF and the actual specifications of the circuit performances. The suitability of the actual reduced functional test set for production test must next be evaluated in terms of its capability of detecting catastrophic and parametric faults.
English

Proceedings of 13th IEEE International Mixed-Signals Testing Workhop (IMSTW'07)
not specified
2007
20-24
IEEE Computer Society
ISBN: 978-972-99181-2-4

13th IEEE International Mixed-Signals Testing Workhop (IMSTW'07)
2007-06-18
Porto
Portugal

analogue-circuit-testing
PACS 85.42