279 articles – 2096 references  [version française]
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Investigation of Electromagnetic Fault Injection Effects on Embedded Cryptosystems
Alberto D. et al
In Proceedings of First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2013) - First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2013), France (2013) [hal-00862773 - version 1]
Hot topic session 4A: Reliability analysis of complex digital systems
Evans A. et al
In Proc. of IEEE 31st VLSI Test Symposium (VTS'13) - IEEE 31st VLSI Test Symposium (VTS'13), United States (2013) [hal-00842825 - version 1]
ADDA: Adaptive Double-sampling Architecture for Highly Flexible Robust Design
Nicolaidis M.
In Proc. of Design Automation and Test in Europe Conference (DATE) - Design Automation and Test in Europe Conference (DATE), Grenoble, France (2013) [hal-00842818 - version 1]
Towards a Hierarchical and Scalable Approach for Modeling the Effects of SETs
Costenaro E. et al
In Proc. of IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE) - IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), United States (2013) [hal-00842816 - version 1]
Iterative Diagnosis for ECC-based Memory Repair
Papavramidou P. et al
In Proc. of IEEE VLSI Test Symposium (VTS) - IEEE VLSI Test Symposium (VTS), United States (2013) [hal-00842320 - version 1]
Reducing Power Dissipation in Memory Repair for High Defect Densities
Papavramidou P. et al
In Proc. of 18th IEEE European Test Symposium (ETS'13) - 18th IEEE European Test Symposium (ETS'13), Avignon, France, May 27-31, France (2013) [hal-00842251 - version 1]
Variability-Aware and Fault-tolerant Self-Adaptive applications for Many-Core chips
Bizot G. et al
In 18TH IEEE European Test Symposium (ETS), Avignon, France, May 27th - 30th - 18TH IEEE European Test Symposium (ETS), France (2013) [hal-00842246 - version 1]
Statistical Modelling of Analog Circuits for Test Metrics Computation
Beznia K. et al
In Proc. of 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) - 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), United Arab Emirates (2013) [hal-00842240 - version 1]
Multivariate Statistical Techniques for Analog Parametric Test Metrics Estimation
Huang K. et al
In 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Abu Dhabi, UAE, March 26-28 - 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Abu Dhabi, UAE, March 26-28, United Arab Emirates (2013) [hal-00842238 - version 1]
Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation
Yahya E. et al
In Proc. of 19th International Symposium on Asynchronous Circuits and Systems (ASYNC) - 19th International Symposium on Asynchronous Circuits and Systems (ASYNC), United States (2013) [hal-00842226 - version 1]
Non-uniform sampling pattern recognition based on atomic decomposition
Le Pelleter T. et al
In Proc. of 10th International Conference on Sampling Theory and Applications (SampTA 2013) - 10th International Conference on Sampling Theory and Applications (SampTA 2013), Germany (2013) [hal-00842215 - version 1]
From System Model Formalization Towards Correct and Efficient HW/SW Design
Jaber M. et al
In 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) - 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), , UAE, March 26-28, United Arab Emirates (2013) [hal-00841753 - version 1]
Low-power signal processing platform based on non-uniform sampling and event-driven circuitry
Le Pelleter T. et al
Dans Design, Automation and Test in Europe (DATE'13) - Design, Automation and Test in Europe (DATE'13), France (2013) [hal-00841614 - version 1]
Clustering Techniques and Statistical Fault Injection for Selective Mitigation of SEUs in Flip-Flops
Evans A. et al
Dans International Symposium on Quality Electronic Design (ISQED) - International Symposium on Quality Electronic Design (ISQED), États-Unis (2013) [hal-00841338 - version 1]
An asynchronous FPGA block with its tech-mapping algorithm dedicated to security applications
Beyrouthy T. et al
International Journal of Reconfigurable Computing 2013, Article ID 517947 (2013) 12 pages [hal-00819126 - version 1]
Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes
Hamdioui S. et al
In Proc. of Design Automation and Test in Europe Conference (Date'13) - Design Automation and Test in Europe Conference (Date'13), France (2013) [hal-00816027 - version 1]
Cramer-Rao lower bounds and maximum likelihood timing synchronization for dirty template UWB communications
Alhakim R. et al
Signal Image and Video Processing Journal 7, 4, July (2013) 741-757 [hal-00672367 - version 1]
fulltext access Génération de séquences de test pour l'accélération d'assertions
Damri L.
Université de Grenoble (17/12/2012), Laurence Pierre (Dir.) [tel-00838669 - version 2]
STAR - Dépôt national des thèses électroniques
Accurate Estimation of Analog Test Metrics With Extreme Circuits
Beznia K. et al
In In IEEE International Conference on Electronics, Circuits, and Systems (ICECS) - In IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Spain (2012) [hal-00765175 - version 1]
A Tool for Statistical Modelling by Means of Copulas of Analog and Mixed-Signal Circuits
Bounceur A. et al
In In 27th conference on Design of Circuits and Integrated Systems (DCIS'12) - In 27th conference on Design of Circuits and Integrated Systems (DCIS'12), France (2012) [hal-00765185 - version 1]