282 articles – 2121 references  [version française]
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A VLSI implementation of parallel fast Fourier transform
VACHER A. et al
Dans Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6. - Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6., France (1994) [hal-00014947 - version 1]
Combinational digit-set converters for hybrid radix-4 arithmetic
Montalvo L.-A. et al
In Proceedings-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.94CH35712. - Proceedings-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.94CH35712., United States (1994) [hal-00014946 - version 1]
CMOS implementation of a hybrid radix-4 divider
Montalvo L.-A. et al
In ESSCIRC-'94.-Twentieth-European-Solid-State-Circuits-Conference.-Proceedings. - ESSCIRC-'94.-Twentieth-European-Solid-State-Circuits-Conference.-Proceedings., Germany (1994) [hal-00014940 - version 1]
On-line hardware implementation for complex exponential and logarithm
Skaf A. et al
In ESSCIRC-'94.-Twentieth-European-Solid-State-Circuits-Conference.-Proceedings. - ESSCIRC-'94.-Twentieth-European-Solid-State-Circuits-Conference.-Proceedings., Germany (1994) [hal-00014939 - version 1]
A process algebra interpretation of a verification oriented overlanguage of VHDL
Bayol C. et al
In Proceedings-EURO-DAC-'94-with-EURO-VHDL-'94-IEEE-Cat.-No.94CH35704. - Proceedings-EURO-DAC-'94-with-EURO-VHDL-'94-IEEE-Cat.-No.94CH35704., France (1994) [hal-00014238 - version 1]
Fault secure property versus strongly code disjoint checkers
Nicolaidis M.
IEEE-Transactions-on-Computer-Aided-Design-of-Integrated-Circuits-and-Systems May ; 13(5) (1994) 651-8 [hal-00013945 - version 1]
Efficient implementations of self-checking multiply and divide arrays
Nicolaidis M. et al
In Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6. - Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6., France (1994) [hal-00013943 - version 1]
Efficient UBIST for RAMs
Nicolaidis M.
In Proceedings-12th-IEEE-VLSI-Test-Symposium-Cat.-No.94TH0645-2. 1994: - Proceedings-12th-IEEE-VLSI-Test-Symposium-Cat.-No.94TH0645-2. 1994:, United States (1994) [hal-00013941 - version 1]
Design for testability of on-line multipliers
Bederr H. et al
In Proceedings-12th-IEEE-VLSI-Test-Symposium-Cat.-No.94TH0645-2. - Proceedings-12th-IEEE-VLSI-Test-Symposium-Cat.-No.94TH0645-2., United States (1994) [hal-00013939 - version 1]
SEU-tolerant SRAM design based on current monitoring
Vargas F. Hernan et al
In Digest-of-Papers.-The-Twenty-Fourth-International-Symposium-on-Fault-Tolerant-Computing-Cat.-No.94CH3441-3. 1994: - Digest-of-Papers.-The-Twenty-Fourth-International-Symposium-on-Fault-Tolerant-Computing-Cat.-No.94CH3441-3. 1994:, United States (1994) [hal-00013937 - version 1]
Trade-offs in scan path and BIST implementations for RAMs
Nicolaidis M. et al
Journal-of-Electronic-Testing:-Theory-and-Applications May-Aug. ; 5(2-3) (1994) 273-83 [hal-00013936 - version 1]
Aliasing-free signature analysis for RAM BIST
Yarmolik V.-N. et al
In Proceedings.-International-Test-Conference-1994-IEEE-Cat.-No.94CH3483-5. - Proceedings.-International-Test-Conference-1994-IEEE-Cat.-No.94CH3483-5., United States (1994) [hal-00013935 - version 1]
Zero aliasing ROM BIST
Kebichi O. et al
Journal-of-Electronic-Testing:-Theory-and-Applications Nov. ; 5(4) (1994) 377-88 [hal-00013934 - version 1]
Strongly fail-safe interfaces based on concurrent checking
Nicolaidis M.
In Proceedings-of-the-Third-Asian-Test-Symposium-Cat.-No.94TH8016. - Proceedings-of-the-Third-Asian-Test-Symposium-Cat.-No.94TH8016., Japan (1994) [hal-00013930 - version 1]
A test methodology applied to cellular logic programmable gate arrays
Duarte R.-O. et al
In Field-Programmable-Logic-Architectures,-Synthesis-and-Applications.-4th-International-Workshop-on-Field-Programmable-Logic-and-Applications,-FPL-'94.-Proceedings. - Field-Programmable-Logic-Architectures,-Synthesis-and-Applications.-4th-International-Workshop-on-Field-Programmable-Logic-and-Applications,-FPL-'94.-Proceedings., Czech Republic (1994) [hal-00013897 - version 1]
Re-engineering hardware specifications by exploiting design semantics
Mir S. et al
In Proceedings of EURO-DAC European Design Automation Conference - Proceedings of EURO-DAC European Design Automation Conference, France (1994) [hal-00013314 - version 1]
Built-in self-test and fault diagnosis of fully differential analogue circuits
Courtois B. et al
In Proceedings of 1994 IEEE International Conference on Computer Aided Design (CAD-94). 6-10 Nov. 1994 - Proceedings of 1994 IEEE International Conference on Computer Aided Design (CAD-94). 6-10 Nov. 1994, United States (1994) [hal-00013312 - version 1]
The design of fast asynchronous adder structures and their implementation using DCVS logic
Renaudin M. et al
In 1994-IEEE-International-Symposium-on-Circuits-and-Systems-Cat.-No.94CH3435-5 - 1994-IEEE-International-Symposium-on-Circuits-and-Systems-Cat.-No.94CH3435-5, United Kingdom (1994) [hal-00012055 - version 1]
Design of SEU-hardened CMOS memory cells: the HIT cell
Bessot D. et al
In RADECS-93 - (1994) [hal-00008260 - version 1]
Accelerating the design process by using architectural synthesis
Kission P. et al
In Proceedings-The-Fifth-International-Workshop-on-Rapid-System-Prototyping.-Shortening-the-Path-from-Specification-to-Prototype- - (1994) [hal-00008151 - version 1]