279 articles – 2093 references  [version française]
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fulltext access Analyse statique de l'effet des erreurs de configuration dans des FGPA configurés par SRAM et amélioration de robustesse
Ferron J.-B.
Université de Grenoble (26/03/2012), Regis Leveugle;Lorena Anghel (Dir.) [tel-00721752 - version 1]
STAR - Dépôt national des thèses électroniques
fulltext access Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs
Cherkaoui A. et al
In Proceedings of Design Automation and Test in Europe (DATE 2012) - Design Automation and Test in Europe (DATE 2012), Germany (2012) [ujm-00667639 - version 1]
N/A : [({datebrevet})]
fulltext access Architectures logicielles pour la radio flexible : intégration d'unités de calcul hétérogènes
Horrein P.-H.
Université de Grenoble (10/01/2012), Frederic Petrot (Dir.) [tel-00680080 - version 1]
STAR - Dépôt national des thèses électroniques
Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode
Possamai Bastos R. et al
Microelectronics Reliability 52, 9-10, September-October (2012) 1781-1786 [hal-00873155 - version 1]
Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode
Possamai Bastos R. et al
In Proc. of 23rd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF) - 23rd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Italy (2012) [hal-00867864 - version 1]
Through-Silicon-Via Built-In Self-Repair for Aggressive 3D Integration
Nicolaidis M. et al
In IEEE 18th International On-Line Testing Symposium (IOLTS) - IEEE 18th International On-Line Testing Symposium (IOLTS), Spain (2012) [hal-00841561 - version 1]
A Standards Based Approach to the Reliability Specification of IP Components
Evans A. et al
In IP-SOC Conference - IP-SOC Conference, France (2012) [hal-00840774 - version 1]
fulltext access An Energy-Efficient Architecture for Nanometric Technologies with Strong Robustness to Process Variability : Design of a GALS node based on a MIPS R2000 processor
Durand S. et al
[hal-00675609 - version 1] (01/06/2013)
Optimizing Construction of Scheduled Data Flow Graph for Online testability
Kamsu Foguem B. et al
The Mediterranean Journal of Computers and Networks 8, 4 (2012) 125-133 [hal-00819170 - version 1]
Design of tracking loop with dirty templates for UWB communication systems
Alhakim R. et al
Signal Image and Video Processing Journal June (2012) 1-7 [hal-00819166 - version 1]
Strain microgauge implementation on cylindrical metal substrates
Yang W. et al
Microelectronic Engineering 97, September (2012) 285-288 [hal-00817861 - version 1]
Pressure and temperature dependence of GaN/AlGaN high electron mobility transistor based sensors on a sapphire membrane
Edwards M.J. et al
PHYSICA STATUS SOLIDI C: CURRENT TOPICS IN SOLID STATE PHYSICS 9, 3-4 (2012) 960-963 [hal-00817852 - version 1]
Microprocessor Soft Error Rate Prediction Based on Cache Memory Analysis
Houssany S. et al
IEEE Transactions on Nuclear Science 59, 4, Part 1 (2012) 980-987 [hal-00817844 - version 1]
Biologically Inspired Robust Tera-Device Processors
Nicolaidis M.
IEEE Design and Test of Computers 29, No.5, September/October (2012) 94-99 [hal-00817030 - version 1]
Case Study of SEU Effects in a Network Processor
Evans A. et al
In Proc. of IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE) - IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), United States (2012) [hal-00815995 - version 1]
Test algorithms for ECC-based memory repair in nanotechnologies
Papavramidou P. et al
In Proc.of IEEE VLSI Test Symposium (VTS) - IEEE VLSI Test Symposium (VTS), United States (2012) [hal-00815986 - version 1]
Designing Robust Single-Chip Massively-Parallel Tera-Device Processors
Nicolaidis M.
In Proc of 4th Design for Reliability Workshop (DFR) - Proc. of 4th Design for Reliability Workshop (DFR), France (2012) [hal-00815969 - version 1]
Cells: A Framework for Designing Robust Tera-Device Processors
Nicolaidis M.
Dans Proc of Workshop on Low Power Design Impact on Test and Reliability (LPonTR) - Workshop on Low Power Design Impact on Test and Reliability (LPonTR), France (2012) [hal-00815963 - version 1]
Experimental Assessment of Cache Memory Soft Error Rate Prediction Technique
Houssany S. et al
In Proc. of 13th European Conference on Radiation and its Effects on Components and Systems (RADECS) - 13th European Conference on Radiation and its Effects on Components and Systems (RADECS), France (2012) [hal-00815960 - version 1]