282 articles – 2123 references  [version française]
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Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip
Dimopulos M. et al
Dans IEEE International On-Line Testing symposium (IOLTS'13) - IEEE International On-Line Testing symposium (IOLTS'13), France (2013) [hal-00997169 - version 1]
BIST for Logic and Local Interconnect Resources in a Novel Mesh of Cluster FPGA
Rehman S.-U. et al
Dans IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), États-Unis (2013) [hal-00982772 - version 1]
Through-Silicon-Via Built-In Self-Repair for Aggressive 3D Integration
Nicolaidis M. et al
In IEEE 18th International On-Line Testing Symposium (IOLTS) - IEEE 18th International On-Line Testing Symposium (IOLTS), Spain (2012) [hal-00841561 - version 1]
A predictive bottom-up hierarchical approach to digital system reliability
Huard V. et al
Dans Proc. of IEEE International Reliability Physics Symposium (IRPS'12) - IEEE International Reliability Physics Symposium (IRPS'12), États-Unis (2012) [hal-00747363 - version 1]
Electromigration degradation mechanism analysis of SnAgCu interconnects for eWLB package
Frank T. et al
Dans Proc. of IEEE International Reliability Physics Symposium (IRPS'12) - IEEE International Reliability Physics Symposium (IRPS'12), États-Unis (2012) [hal-00747359 - version 1]
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis
Pasca V. et al
Journal of Electronic Testing: Theory and Application 28 (2012) Online First™, 3 August [hal-00744561 - version 1]
Design for Test and Reliability in Ultimate CMOS
Nicolaidis M. et al
Dans Proc. of Design, Automation and Test in Europe (DATE'12) - Design, Automation and Test in Europe (DATE'12), Allemagne (2012) [hal-00688282 - version 1]
On the Dependability of 3D Interconnects
Anghel L.
Dans Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'12) - Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'12), France (2012) [hal-00677047 - version 1]
Towards Low-cost Soft Error Mitigation in SRAM-based FPGAs: a Case Study on AT40K
Ferron J. et al
Dans Proc. of 3rd IEEE Latin American Symposium on Circuits and Systems (LASCAS'12) - 3rd IEEE Latin American Symposium on Circuits and Systems (LASCAS'12), Mexique (2012) [hal-00676825 - version 1]
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
Pasca V. et al
Journal of Electronic Testing 28, 1 (2012) 137-150 [hal-00650169 - version 1]
Criticality of Configuration Bits in SRAM-based FPGAs: Predictive Analysis and Experimental Results
Anghel L. et al
Dans Proc. of Workshop on Design for Reliability and Variability (DRVW'11) - Workshop on Design for Reliability and Variability (DRVW'11), États-Unis (2011) [hal-00624239 - version 1]
Bottom-up digital system-level reliability modeling
Amador N.R. et al
Dans Custom Integrated Circuits Conference (CICC'11), San Jose, Ca., USA, 19-21 September - Custom Integrated Circuits Conference (CICC'11), États-Unis (2011) [hal-00651936 - version 1]
Electromigration Behavior of 3D-IC TSV
Frank T. et al
Dans Proc. of Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D IC), in conjuction with ITC - Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D IC), in conjuction with ITC, États-Unis (2011) [hal-00651930 - version 1]
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor
Yu H. et al
Dans Proc. of 16th IEEE European Test Symposium (ETS'11) - 16th IEEE European Test Symposium (ETS'11), Norvège (2011) [hal-00651920 - version 1]
I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems
Nicolaidis M. et al
Dans Proc. of 16th IEEE European Test Symposium (ETS'11) - 16th IEEE European Test Symposium (ETS'11), Norvège (2011) [hal-00651916 - version 1]
Memory BIST with address programmability
Fradi A. et al
Dans Proc. of IEEE international On Line Testing Symposium (IOLT'11) - IEEE international On Line Testing Symposium (IOLT'11), Grèce (2011) [hal-00651913 - version 1]
Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis
Pasca V. et al
Dans Proc. of IEEE Latin America Test Symposium Workshop (LATW'11) - IEEE Latin America Test Symposium Workshop (LATW'11), Brésil (2011) [hal-00651437 - version 1]
Designing cost-effective robust systems by accurate reliability modeling
Anghel L. et al
Dans Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'11) - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'11), Canada (2011) [hal-00651413 - version 1]
On the Dependability of 3D Interconnects
Anghel L. et al
Dans Proc. of Dependability Issues in Deep-submicron Technologies Workshop (DDT'11) - Dependability Issues in Deep-submicron Technologies Workshop (DDT'11), Norvège (2011) [hal-00650195 - version 1]
Adaptive inter-layer message routing in 3D networks-on-chip
Rusu C. et al
Microprocessors and Microsystems 35, 7 (2011) 613-631 [hal-00650162 - version 1]