248 articles – 2008 Notices  [english version]
Fiche détaillée Communications avec actes
IEEE International Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems (DFT'11), Vancouver : Canada (2011)
A Practical Approach to Single Event Transients Analysis for Highly Complex Designs
D. Alexandrescu1, 2, E. Costenaro2, M. Nicolaidis1

Single Event Transients are considerably more difficult to model, simulate and analyze than the closely-related Single Event Upsets. The work environment may cause a myriad of distinctive transient pulses in various cell types that are used in widely different configurations. We present practical methods to help characterizing the standard cell library using dedicated tools and results from radiation testing. Furthermore, we analyze the SET propagation in logic networks using a standard (reference) serial fault simulation approach and an accelerated fault simulation technique, taking in account both logic and temporal considerations. The accelerated method provides similar results as the reference approach while offering a considerable increase in the simulation speed. However, the simulation approach may not be feasible for large (multi-million cells) designs that could benefit from static analysis methods. We benchmark the results of a static, probabilistic approach against the reference and accelerated methods. Finally, we discuss the integration of the SET analysis in a complete Soft Error Rate analysis flow.
1 :  TIMA - Techniques of Informatics and Microelectronics for integrated systems Architecture
2 :  IROC TECHNOLOGIES - iROc Technologies
Integrated Circuits – transient analysis – transistor – circuits..........